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Re: [PATCH v3 27/30] target/ppc: Move D/DS/X-form integer loads to decod


From: Matheus K. Ferst
Subject: Re: [PATCH v3 27/30] target/ppc: Move D/DS/X-form integer loads to decodetree
Date: Mon, 3 May 2021 09:28:01 -0300
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1

On 30/04/2021 21:50, Richard Henderson wrote:
On 4/30/21 4:54 PM, Matheus K. Ferst wrote:
The only difference between those two is tcg_gen_addi_tl/tcg_gen_movi_tl and tcg_gen_add_tl/tcg_gen_mov_tl. We could do this in a single method if we tcg_const_tl(a->si) in do_ldst_D. I'm not sure about the costs involved, and we'd need to tcg_temp_free it. If you want to give it a look, I did some tests on https://github.com/ppc64/qemu/tree/ferst-tcg-decodetree64 .

I guess it works, but it feels ugly with the comparison vs cpu_gpr[0]. Maybe pass in rt and ra as integers, and only pass in rb/si as TCGv addend?


I tried that first and it looked just as weird, but if you prefer I'll change it back. We could also hide the ugliness in a helper e.g. bool gpr_is_zero(TCGv).

The upper-case argument names clash with docs/devel/style.rst.


Good call, I'll fix this before push this branch again;

You can use tcg_constant_tl() to grab a hashed constant that need not be freed.


Then we could

> return do_ldst(ctx, cpu_gpr[a->rt], a->ra?cpu->gpr[a->ra]:tcg_const_tl(0), ...

At the cost of always calling tcg_gen_add_tl and repeating the RA=0 logic in do_ldst_X and do_ldst_D.

BTW, I thought I had a comment about PLS being used for both MLS and 8LS.  I guess that must have gotten lost at some point.  If you go with your renaming to MLS, you'll want a different comment about PLD et al.


r~

Don't mind that, it was a bad idea, I gave up on this change while rebasing v3.

Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>



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