[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 4/7] target/ppc: Add support for paired vector load/store instruc
|
From: |
Gustavo Romero |
|
Subject: |
[PATCH 4/7] target/ppc: Add support for paired vector load/store instructions |
|
Date: |
Mon, 5 Oct 2020 01:03:16 -0300 |
From: Michael Roth <mdroth@linux.vnet.ibm.com>
This adds support for the following load/store instructions for paired
vector registers:
lxvp, plxvp, lxvpx
stxvp, pstxvp, stxvpx
Signed-off-by: Michael Roth <mroth@lamentation.net>
[ gromero: - fix in helper_load_paired_vec(), for LE
- fix in helper_store_paired_vec(), for LE ]
Sgined-off-by: Gustavo Romero <gromero@linux.ibm.com>
---
target/ppc/helper.h | 3 ++
target/ppc/internal.h | 7 +++
target/ppc/mem_helper.c | 61 ++++++++++++++++++++++++++
target/ppc/translate.c | 6 +++
target/ppc/translate/vsx-impl.c.inc | 66 +++++++++++++++++++++++++++++
5 files changed, 143 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6a4dccf70c..e8ecd2e878 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -279,6 +279,9 @@ DEF_HELPER_4(lxvl, void, env, tl, vsr, tl)
DEF_HELPER_4(lxvll, void, env, tl, vsr, tl)
DEF_HELPER_4(stxvl, void, env, tl, vsr, tl)
DEF_HELPER_4(stxvll, void, env, tl, vsr, tl)
+/* lxvp/stxvp, plxvp/pstxvp, lxvpx/stxvpx */
+DEF_HELPER_4(store_paired_vec, void, env, tl, vsr, vsr)
+DEF_HELPER_4(load_paired_vec, void, env, tl, vsr, vsr)
#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index dc4aff863c..de88c3abe7 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -80,6 +80,12 @@ static inline int16_t name(uint32_t opcode)
\
(((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2));
\
}
+#define EXTRACT_HELPER_SPLIT_SHIFTED(name, shift1, nb1, shift2, nb2, shift3) \
+static inline uint32_t name(uint32_t opcode) \
+{ \
+ return extract32(opcode, shift1, nb1) << (nb2 + shift3) | \
+ extract32(opcode, shift2, nb2) << shift3; \
+}
/* Opcode part 1 */
EXTRACT_HELPER(opc1, 26, 6);
@@ -226,6 +232,7 @@ EXTRACT_HELPER(SP, 19, 2);
EXTRACT_HELPER(IMM8, 11, 8);
EXTRACT_HELPER(DCMX, 16, 7);
EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
+EXTRACT_HELPER_SPLIT_SHIFTED(xTp, 21, 1, 22, 4, 1);
void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 98f589552b..8d35a19c68 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -532,6 +532,67 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
#undef I
#undef LVE
+#ifdef TARGET_PPC64
+void helper_load_paired_vec(CPUPPCState *env, target_ulong addr,
+ ppc_vsr_t *xt0, ppc_vsr_t *xt1)
+{
+ ppc_vsr_t t0, t1;
+ int i;
+
+ t0.s128 = int128_zero();
+ t1.s128 = int128_zero();
+
+ if (msr_le) {
+ for (i = 0; i < 16; i++) {
+ t1.VsrB(15 - i) = cpu_ldub_data_ra(env, addr, GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ for (i = 0; i < 16; i++) {
+ t0.VsrB(15 - i) = cpu_ldub_data_ra(env, addr, GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ } else { // TODO: check if it's correct for BE.
+ for (i = 0; i < 16; i++) {
+ t0.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ for (i = 0; i < 16; i++) {
+ t1.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ }
+
+ *xt0 = t0;
+ *xt1 = t1;
+}
+
+void helper_store_paired_vec(CPUPPCState *env, target_ulong addr,
+ ppc_vsr_t *xt0, ppc_vsr_t *xt1)
+{
+ int i;
+
+ if (msr_le) {
+ for (i = 0; i < 16; i++) {
+ cpu_stb_data_ra(env, addr, xt1->VsrB(15 - i), GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ for (i = 0; i < 16; i++) {
+ cpu_stb_data_ra(env, addr, xt0->VsrB(15 - i), GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ } else { // TODO: check if it's correct for BE.
+ for (i = 0; i < 16; i++) {
+ cpu_stb_data_ra(env, addr, xt0->VsrB(i), GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ for (i = 0; i < 16; i++) {
+ cpu_stb_data_ra(env, addr, xt1->VsrB(i), GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ }
+}
+#endif /* TARGET_PPC64 */
+
#ifdef TARGET_PPC64
#define GET_NB(rb) ((rb >> 56) & 0xFF)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 82376b50ff..e2fe0c1243 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7392,6 +7392,12 @@ GEN_HANDLER_E_PREFIXED(pstq, 0x3c, 0xFF, 0xFF,
0x00000000, PPC_64B, PPC2_ISA310)
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
/* handles stfdp, lxv, stxsd, stxssp, stxv */
GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E_PREFIXED(plxvp, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_NONE,
PPC2_ISA310),
+GEN_HANDLER_E_PREFIXED(pstxvp, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_NONE,
PPC2_ISA310),
+/* handles lxvp, stxvp */
+GEN_HANDLER_E(dqform6, 0x6, 0x0, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA310),
+GEN_HANDLER_E(lxvpx, 0x1F, 0xD, 0xA, 0x00000000, PPC_NONE, PPC2_ISA310),
+GEN_HANDLER_E(stxvpx, 0x1F, 0xD, 0xE, 0x00000000, PPC_NONE, PPC2_ISA310),
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index b518de46db..6640b7ae05 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -376,6 +376,72 @@ VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
#endif
+#ifdef TARGET_PPC64
+
+static void gen_dqform6(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_ptr xt0, xt1;
+
+ EA = tcg_temp_new();
+ xt0 = gen_vsr_ptr(xTp(ctx->opcode));
+ xt1 = gen_vsr_ptr(xTp(ctx->opcode) + 1);
+ gen_set_access_type(ctx, ACCESS_INT);
+ gen_addr_imm_index(ctx, EA, 0x0F);
+
+ if (extract32(ctx->opcode, 0, 4) == 1) {
+ /* stxvp */
+ gen_helper_store_paired_vec(cpu_env, EA, xt0, xt1);
+ } else {
+ /* lxvp */
+ gen_helper_load_paired_vec(cpu_env, EA, xt0, xt1);
+ }
+
+ tcg_temp_free(EA);
+ tcg_temp_free_ptr(xt0);
+ tcg_temp_free_ptr(xt1);
+}
+
+#define VSX_VECTOR_LOAD_STORE_PAIRED(name, dform, op) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_ptr xt0, xt1; \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ \
+ EA = tcg_temp_new(); \
+ xt0 = gen_vsr_ptr(xTp(ctx->opcode)); \
+ xt1 = gen_vsr_ptr(xTp(ctx->opcode) + 1); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ \
+ if (dform) { \
+ /* pstxvp, plxvp, 8LS, D-form */ \
+ if (gen_addr_imm34_index(ctx, EA)) { \
+ goto out; \
+ } \
+ } else { \
+ /* lxvpx, stxvpx, X-form */ \
+ gen_addr_reg_index(ctx, EA); \
+ } \
+ \
+ gen_helper_##op##_paired_vec(cpu_env, EA, xt0, xt1); \
+out: \
+ tcg_temp_free(EA); \
+ tcg_temp_free_ptr(xt0); \
+ tcg_temp_free_ptr(xt1); \
+}
+
+VSX_VECTOR_LOAD_STORE_PAIRED(plxvp, 1, load)
+VSX_VECTOR_LOAD_STORE_PAIRED(pstxvp, 1, store)
+VSX_VECTOR_LOAD_STORE_PAIRED(lxvpx, 0, load)
+VSX_VECTOR_LOAD_STORE_PAIRED(stxvpx, 0, store)
+
+#endif
+
#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.17.1
- [PATCH 1/7] target/ppc: Add infrastructure for prefixed instructions, Gustavo Romero, 2020/10/05
- [PATCH 3/7] tests/tcg: Add tests for prefixed load/store instructions, Gustavo Romero, 2020/10/05
- [PATCH 4/7] target/ppc: Add support for paired vector load/store instructions,
Gustavo Romero <=
- [PATCH 5/7] tests/tcg: Add tests for paired vector load/store instructions, Gustavo Romero, 2020/10/05
- [PATCH 6/7] target/ppc: Add support for prefixed load/store FP instructions, Gustavo Romero, 2020/10/05
- [PATCH 7/7] tests/tcg: Add tests for prefixed load/store FP instructions, Gustavo Romero, 2020/10/05
- Re: [PATCH 1/7] target/ppc: Add infrastructure for prefixed instructions, David Gibson, 2020/10/08