[PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions

[Lijun Pan]

This patch series add several newly introduced 32/64-bit vector
instructions in Power ISA 3.1. The newly added instructions are
flagged as ISA300 temporarily in vmx-ops.inc.c and vmx-impl.inc.c
to make them compile and function since Power ISA 3.1, together
with next generation processor, has not been fully enabled in QEMU
yet. When Power ISA 3.1 and next generation processor are fully
supported, the flags should be changed.

Lijun Pan (6):
  target/ppc: add byte-reverse br[dwh] instructions
  target/ppc: add vmulld instruction
  targetc/ppc: add vmulh{su}w instructions
  target/ppc: add vmulh{su}d instructions
  fix the prototype of muls64/mulu64
  target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions

 include/qemu/host-utils.h           |  4 +-
 target/ppc/helper.h                 | 13 ++++++
 target/ppc/int_helper.c             | 58 +++++++++++++++++++++++++
 target/ppc/translate.c              | 65 +++++++++++++++++++++++++++++
 target/ppc/translate/vmx-impl.inc.c | 24 +++++++++++
 target/ppc/translate/vmx-ops.inc.c  | 22 ++++++++--
 6 files changed, 180 insertions(+), 6 deletions(-)

-- 
2.23.0