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[PULL 30/45] target/ppc: Fix rlwinm on ppc64
From: |
David Gibson |
Subject: |
[PULL 30/45] target/ppc: Fix rlwinm on ppc64 |
Date: |
Tue, 17 Mar 2020 21:04:08 +1100 |
From: Vitaly Chikunov <address@hidden>
rlwinm cannot just AND with Mask if shift value is zero on ppc64 when
Mask Begin is greater than Mask End and high bits are set to 1.
Note that PowerISA 3.0B says that for `rlwinm' ROTL32 is used, and
ROTL32 is defined (in 3.3.14) so that rotated value should have two
copies of lower word of the source value.
This seems to be another incarnation of the fix from 820724d170
("target-ppc: Fix rlwimi, rlwinm, rlwnm again"), except I leave
optimization when Mask value is less than 32 bits.
Fixes: 7b4d326f47 ("target-ppc: Use the new deposit and extract ops")
Cc: address@hidden
Signed-off-by: Vitaly Chikunov <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 36fa27367c..127c82a24e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1938,15 +1938,17 @@ static void gen_rlwinm(DisasContext *ctx)
me += 32;
#endif
mask = MASK(mb, me);
- if (sh == 0) {
- tcg_gen_andi_tl(t_ra, t_rs, mask);
- } else if (mask <= 0xffffffffu) {
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t0, t_rs);
- tcg_gen_rotli_i32(t0, t0, sh);
- tcg_gen_andi_i32(t0, t0, mask);
- tcg_gen_extu_i32_tl(t_ra, t0);
- tcg_temp_free_i32(t0);
+ if (mask <= 0xffffffffu) {
+ if (sh == 0) {
+ tcg_gen_andi_tl(t_ra, t_rs, mask);
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, t_rs);
+ tcg_gen_rotli_i32(t0, t0, sh);
+ tcg_gen_andi_i32(t0, t0, mask);
+ tcg_gen_extu_i32_tl(t_ra, t0);
+ tcg_temp_free_i32(t0);
+ }
} else {
#if defined(TARGET_PPC64)
tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
--
2.24.1
- [PULL 19/45] spapr: Don't attempt to clamp RMA to VRMA constraint, (continued)
- [PULL 19/45] spapr: Don't attempt to clamp RMA to VRMA constraint, David Gibson, 2020/03/17
- [PULL 31/45] ppc/spapr: Move GPRs setup to one place, David Gibson, 2020/03/17
- [PULL 21/45] spapr: Clean up RMA size calculation, David Gibson, 2020/03/17
- [PULL 01/45] pseries: Update SLOF firmware image, David Gibson, 2020/03/17
- [PULL 25/45] hw/scsi/spapr_vscsi: Introduce req_iu() helper, David Gibson, 2020/03/17
- [PULL 29/45] spapr/xive: use SPAPR_IRQ_IPI to define IPI ranges exposed to the guest, David Gibson, 2020/03/17
- [PULL 22/45] hw/scsi/viosrp: Add missing 'hw/scsi/srp.h' include, David Gibson, 2020/03/17
- [PULL 28/45] hw/scsi/spapr_vscsi: Convert debug fprintf() to trace event, David Gibson, 2020/03/17
- [PULL 26/45] hw/scsi/spapr_vscsi: Do not mix SRP IU size with DMA buffer size, David Gibson, 2020/03/17
- [PULL 36/45] spapr: Rename DT functions to newer naming convention, David Gibson, 2020/03/17
- [PULL 30/45] target/ppc: Fix rlwinm on ppc64,
David Gibson <=
- [PULL 40/45] ppc/spapr: Fix FWNMI machine check interrupt delivery, David Gibson, 2020/03/17
- [PULL 37/45] ppc/spapr: Fix FWNMI machine check failure handling, David Gibson, 2020/03/17
- [PULL 35/45] spapr: Move creation of ibm,architecture-vec-5 property, David Gibson, 2020/03/17
- [PULL 43/45] ppc/spapr: Implement FWNMI System Reset delivery, David Gibson, 2020/03/17
- [PULL 33/45] spapr/rtas: Reserve space for RTAS blob and log, David Gibson, 2020/03/17
- [PULL 39/45] ppc/spapr: Add FWNMI System Reset state, David Gibson, 2020/03/17
- [PULL 41/45] ppc/spapr: Allow FWNMI on TCG, David Gibson, 2020/03/17
- [PULL 38/45] ppc/spapr: Change FWNMI names, David Gibson, 2020/03/17
- [PULL 34/45] spapr: Move creation of ibm, dynamic-reconfiguration-memory dt node, David Gibson, 2020/03/17
- [PULL 44/45] ppc/spapr: Ignore common "ibm,nmi-interlock" Linux bug, David Gibson, 2020/03/17