[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 10/45] spapr, ppc: Remove VPM0/RMLS hacks for POWER9
From: |
David Gibson |
Subject: |
[PULL 10/45] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 |
Date: |
Tue, 17 Mar 2020 21:03:48 +1100 |
For the "pseries" machine, we use "virtual hypervisor" mode where we
only model the CPU in non-hypervisor privileged mode. This means that
we need guest physical addresses within the modelled cpu to be treated
as absolute physical addresses.
We used to do that by clearing LPCR[VPM0] and setting LPCR[RMLS] to a high
limit so that the old offset based translation for guest mode applied,
which does what we need. However, POWER9 has removed support for that
translation mode, which meant we had some ugly hacks to keep it working.
We now explicitly handle this sort of translation for virtual hypervisor
mode, so the hacks aren't necessary. We don't need to set VPM0 and RMLS
from the machine type code - they're now ignored in vhyp mode. On the cpu
side we don't need to allow LPCR[RMLS] to be set on POWER9 in vhyp mode -
that was only there to allow the hack on the machine side.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
---
hw/ppc/spapr_cpu_core.c | 10 +---------
target/ppc/mmu-hash64.c | 8 --------
2 files changed, 1 insertion(+), 17 deletions(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index d09125d9af..36ed3a2b66 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -50,22 +50,14 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
* the settings below ensure proper operations with TCG in absence of
* a real hypervisor.
*
- * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
- * real mode accesses, which thankfully defaults to 0 and isn't
- * accessible in guest mode.
- *
* Disable Power-saving mode Exit Cause exceptions for the CPU, so
* we don't get spurious wakups before an RTAS start-cpu call.
* For the same reason, set PSSCR_EC.
*/
- lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
+ lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
lpcr |= LPCR_LPES0 | LPCR_LPES1;
env->spr[SPR_PSSCR] |= PSSCR_EC;
- /* Set RMLS to the max (ie, 16G) */
- lpcr &= ~LPCR_RMLS;
- lpcr |= 1ull << LPCR_RMLS_SHIFT;
-
ppc_store_lpcr(cpu, lpcr);
/* Set a full AMOR so guest can use the AMR as it sees fit */
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index e372c42add..caf47ad6fc 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1126,14 +1126,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
(LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
- /*
- * If we have a virtual hypervisor, we need to bring back RMLS. It
- * doesn't exist on an actual P9 but that's all we know how to
- * configure with softmmu at the moment
- */
- if (cpu->vhyp) {
- lpcr |= (val & LPCR_RMLS);
- }
break;
default:
g_assert_not_reached();
--
2.24.1
- [PULL 00/45] ppc-for-5.0 queue 20200317, David Gibson, 2020/03/17
- [PULL 04/45] spapr: Fix Coverity warning while validating nvdimm options, David Gibson, 2020/03/17
- [PULL 02/45] spapr: Handle pending hot plug/unplug requests at CAS, David Gibson, 2020/03/17
- [PULL 03/45] ppc: Officially deprecate the CPU "compat" property, David Gibson, 2020/03/17
- [PULL 05/45] hw/ppc/pnv: Fix typo in comment, David Gibson, 2020/03/17
- [PULL 10/45] spapr, ppc: Remove VPM0/RMLS hacks for POWER9,
David Gibson <=
- [PULL 06/45] ppc: Remove stub support for 32-bit hypervisor mode, David Gibson, 2020/03/17
- [PULL 08/45] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU, David Gibson, 2020/03/17
- [PULL 07/45] ppc: Remove stub of PPC970 HID4 implementation, David Gibson, 2020/03/17
- [PULL 12/45] target/ppc: Use class fields to simplify LPCR masking, David Gibson, 2020/03/17
- [PULL 09/45] target/ppc: Introduce ppc_hash64_use_vrma() helper, David Gibson, 2020/03/17
- [PULL 13/45] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS], David Gibson, 2020/03/17
- [PULL 11/45] target/ppc: Remove RMOR register from POWER9 & POWER10, David Gibson, 2020/03/17
- [PULL 14/45] target/ppc: Correct RMLS table, David Gibson, 2020/03/17
- [PULL 23/45] hw/scsi/spapr_vscsi: Use SRP_MAX_IU_LEN instead of sizeof flexible array, David Gibson, 2020/03/17
- [PULL 15/45] target/ppc: Only calculate RMLS derived RMA limit on demand, David Gibson, 2020/03/17