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[Qemu-ppc] [PATCH v4 22/25] ppc/xive: Introduce a xive_os_cam_decode() h
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v4 22/25] ppc/xive: Introduce a xive_os_cam_decode() helper |
Date: |
Wed, 18 Sep 2019 18:06:42 +0200 |
The OS CAM line has a special encoding exploited by the HW. Provide a
helper routine to hide the details to the TIMA command handlers. This
also clarifies the endian ness of different variables : 'qw1w2' is
big-endian and 'cam' is native.
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/intc/xive.c | 35 ++++++++++++++++++++++++++---------
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index dfae584a319f..cdc4ea8b0e51 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -342,14 +342,29 @@ static void xive_tm_set_os_pending(XivePresenter *xptr,
XiveTCTX *tctx,
xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
}
+static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
+ uint32_t *nvt_idx, bool *vo)
+{
+ *nvt_blk = xive_nvt_blk(cam);
+ *nvt_idx = xive_nvt_idx(cam);
+ *vo = !!(cam & TM_QW1W2_VO);
+}
+
static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, unsigned size)
{
- uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
- uint32_t qw1w2;
+ uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
+ uint32_t qw1w2_new;
+ uint32_t cam = be32_to_cpu(qw1w2);
+ uint8_t nvt_blk;
+ uint32_t nvt_idx;
+ bool vo;
- qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0);
- memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+ xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
+
+ /* Invalidate CAM line */
+ qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
+ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
return qw1w2;
}
@@ -387,13 +402,15 @@ static void xive_tctx_need_resend(XiveRouter *xrtr,
XiveTCTX *tctx,
static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size)
{
- uint32_t qw1w2 = value;
- uint8_t nvt_blk = xive_nvt_blk(qw1w2);
- uint32_t nvt_idx = xive_nvt_idx(qw1w2);
- bool vo = !!(qw1w2 & TM_QW1W2_VO);
+ uint32_t cam = value;
+ uint32_t qw1w2 = cpu_to_be32(cam);
+ uint8_t nvt_blk;
+ uint32_t nvt_idx;
+ bool vo;
+
+ xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
/* First update the registers */
- qw1w2 = cpu_to_be32(qw1w2);
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
/* Check the interrupt pending bits */
--
2.21.0
- [Qemu-ppc] [PATCH v4 12/25] ppc/xive: Remove the get_tctx() XiveRouter handler, (continued)
- [Qemu-ppc] [PATCH v4 12/25] ppc/xive: Remove the get_tctx() XiveRouter handler, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 13/25] ppc/xive: Introduce a xive_tctx_ipb_update() helper, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 14/25] ppc/xive: Introduce helpers for the NVT id, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 15/25] ppc/xive: Synthesize interrupt from the saved IPB in the NVT, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 16/25] ppc/pnv: Remove pnv_xive_vst_size() routine, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 17/25] ppc/pnv: Dump the XIVE NVT table, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 18/25] ppc/pnv: Skip empty slots of the XIVE NVT table, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 19/25] ppc/pnv: Introduce a pnv_xive_block_id() helper, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 20/25] ppc/pnv: Extend XiveRouter with a get_block_id() handler, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 21/25] ppc/pnv: Quiesce some XIVE errors, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 22/25] ppc/xive: Introduce a xive_os_cam_decode() helper,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v4 23/25] ppc/xive: Check V bit in TM_PULL_POOL_CTX, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 24/25] ppc/pnv: Improve trigger data definition, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 25/25] ppc/pnv: Use the EAS trigger bit when triggering an interrupt from PSI, Cédric Le Goater, 2019/09/18