Re: [Qemu-ppc] [PATCH v3 00/18] ppc/pnv: add XIVE support for KVM guests

[Cédric Le Goater]

On 31/07/2019 16:12, Cédric Le Goater wrote:
> Hello,
> 
> The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
> acts as an hypervisor (L0). Supporting emulation of KVM to run guests
> (L1) requires a few more extensions, among which guest support for the
> XIVE interrupt controller on POWER9 processor.
> 
> The following changes add new per-CPU PowerNV machines and extend the
> XIVE models with the new XiveFabric and XivePresenter interfaces to
> provide support for XIVE escalations and interrupt resend. This
> mechanism is used by XIVE to notify the hypervisor that a vCPU is not
> dispatched on a HW thread. Tested on a QEMU PowerNV machine and a
> simple QEMU pseries guest doing network on a local bridge.
> 
> The XIVE interrupt controller offers a way to increase the XIVE
> resources per chip by configuring multiple XIVE blocks on a chip. This
> is not currently supported by the model. However, some configurations,
> such as OPAL/skiboot, use one block-per-chip configuration with some
> optimizations. One of them is to override the hardwired chip ID by the
> block id in the PowerBUS operations and for CAM line compares. This
> patchset improves the support for this setup. Tested with 4 chips.

David,

Do you want me to resend this patchset ? or you just didn't have time
to look at it ?  

Patch 16 has changed a little since. The get_block_id() handler has 
moved to the XiveRouterClass.


Thanks,

Thanks,

C.