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[Qemu-ppc] [PATCH v3 09/18] ppc/xive: Move the TIMA operations to the co
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v3 09/18] ppc/xive: Move the TIMA operations to the controller model |
Date: |
Wed, 31 Jul 2019 16:12:24 +0200 |
This also removes the need of the get_tctx() XiveRouter handler in the
core XIVE framework.
Signed-off-by: Cédric Le Goater <address@hidden>
---
include/hw/ppc/xive.h | 3 ---
hw/intc/pnv_xive.c | 48 ++++++++++++++++++++++++++++++-------------
hw/intc/spapr_xive.c | 41 +++++++++++++++++++++++++++---------
hw/intc/xive.c | 36 --------------------------------
4 files changed, 65 insertions(+), 63 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index ba43a4a129d9..b34e2ad43a82 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -352,7 +352,6 @@ typedef struct XiveRouterClass {
XiveNVT *nvt);
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
- XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
} XiveRouterClass;
int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
@@ -365,7 +364,6 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
uint32_t nvt_idx,
XiveNVT *nvt);
int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
-XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
/*
@@ -463,7 +461,6 @@ typedef struct XiveENDSource {
#define XIVE_TM_OS_PAGE 0x2
#define XIVE_TM_USER_PAGE 0x3
-extern const MemoryRegionOps xive_tm_ops;
void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
uint64_t value, unsigned size);
uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index e598857359d8..982f5eef380c 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -485,18 +485,6 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
return xive;
}
-static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- PnvXive *xive = pnv_xive_tm_get_xive(cpu);
-
- if (!xive) {
- return NULL;
- }
-
- return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
-}
-
/*
* The internal sources (IPIs) of the interrupt controller have no
* knowledge of the XIVE chip on which they reside. Encode the block
@@ -1475,6 +1463,39 @@ static const MemoryRegionOps xive_tm_indirect_ops = {
},
};
+static void pnv_xive_tm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size);
+}
+
+static uint64_t pnv_xive_tm_read(void *opaque, hwaddr offset, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size);
+}
+
+const MemoryRegionOps pnv_xive_tm_ops = {
+ .read = pnv_xive_tm_read,
+ .write = pnv_xive_tm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
/*
* Interrupt controller XSCOM region.
*/
@@ -1832,7 +1853,7 @@ static void pnv_xive_realize(DeviceState *dev, Error
**errp)
"xive-pc", PNV9_XIVE_PC_SIZE);
/* Thread Interrupt Management Area (Direct) */
- memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops,
+ memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops,
xive, "xive-tima", PNV9_XIVE_TM_SIZE);
qemu_register_reset(pnv_xive_reset, dev);
@@ -1888,7 +1909,6 @@ static void pnv_xive_class_init(ObjectClass *klass, void
*data)
xrc->write_end = pnv_xive_write_end;
xrc->get_nvt = pnv_xive_get_nvt;
xrc->write_nvt = pnv_xive_write_nvt;
- xrc->get_tctx = pnv_xive_get_tctx;
xnc->notify = pnv_xive_notify;
xpc->match_nvt = pnv_xive_match_nvt;
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index beb5049ad9da..4abb099d341c 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -219,6 +219,35 @@ void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx)
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4);
}
+static void spapr_xive_tm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx;
+
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
+}
+
+static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned size)
+{
+ XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx;
+
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
+}
+
+const MemoryRegionOps spapr_xive_tm_ops = {
+ .read = spapr_xive_tm_read,
+ .write = spapr_xive_tm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
static void spapr_xive_end_reset(XiveEND *end)
{
memset(end, 0, sizeof(*end));
@@ -328,8 +357,8 @@ static void spapr_xive_realize(DeviceState *dev, Error
**errp)
qemu_register_reset(spapr_xive_reset, dev);
/* TIMA initialization */
- memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive,
- "xive.tima", 4ull << TM_SHIFT);
+ memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops,
+ xive, "xive.tima", 4ull << TM_SHIFT);
sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio);
/*
@@ -412,13 +441,6 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t
nvt_blk,
g_assert_not_reached();
}
-static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
-
- return spapr_cpu_state(cpu)->tctx;
-}
-
static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
@@ -546,7 +568,6 @@ static void spapr_xive_class_init(ObjectClass *klass, void
*data)
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
xrc->write_nvt = spapr_xive_write_nvt;
- xrc->get_tctx = spapr_xive_get_tctx;
xpc->match_nvt = spapr_xive_match_nvt;
}
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 9ca015969143..6f74b4dcbbd4 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -480,35 +480,6 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX
*tctx, hwaddr offset,
return xive_tm_raw_read(tctx, offset, size);
}
-static void xive_tm_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
-{
- XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
-
- xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
-}
-
-static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
-{
- XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
-
- return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
-}
-
-const MemoryRegionOps xive_tm_ops = {
- .read = xive_tm_read,
- .write = xive_tm_write,
- .endianness = DEVICE_BIG_ENDIAN,
- .valid = {
- .min_access_size = 1,
- .max_access_size = 8,
- },
- .impl = {
- .min_access_size = 1,
- .max_access_size = 8,
- },
-};
-
static char *xive_tctx_ring_print(uint8_t *ring)
{
uint32_t w2 = xive_tctx_word2(ring);
@@ -1277,13 +1248,6 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t
nvt_blk, uint32_t nvt_idx,
return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
}
-XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
-{
- XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
-
- return xrc->get_tctx(xrtr, cs);
-}
-
/*
* Encode the HW CAM line in the block group mode format :
*
--
2.21.0
- [Qemu-ppc] [PATCH v3 00/18] ppc/pnv: add XIVE support for KVM guests, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 02/18] tests/boot-serial-test: add support for all the PowerNV machines, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 01/18] ppc/pnv: Introduce PowerNV machines with fixed CPU models, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 03/18] ppc/xive: Introduce the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 04/18] ppc/pnv: Implement the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 05/18] ppc/spapr: Implement the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 06/18] ppc/xive: Use the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 07/18] ppc/xive: Extend the TIMA operation with a XivePresenter parameter, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 08/18] ppc/pnv: Clarify how the TIMA is accessed on a multichip system, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 09/18] ppc/xive: Move the TIMA operations to the controller model,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v3 10/18] ppc/xive: Introduce a xive_tctx_ipb_update() helper, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 11/18] ppc/xive: Synthesize interrupt from the saved IPB in the NVT, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 12/18] ppc/pnv: Remove pnv_xive_vst_size() routine, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 13/18] ppc/pnv: Dump the XIVE NVT table, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 14/18] ppc/pnv: Skip empty slots of the XIVE NVT table, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 15/18] ppc/pnv: Introduce a pnv_xive_block_id() helper, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 16/18] ppc/pnv: Extend XivePresenter with a get_block_id() handler, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 17/18] ppc/pnv: Quiesce some XIVE errors, Cédric Le Goater, 2019/07/31
- [Qemu-ppc] [PATCH v3 18/18] ppc/xive: Introduce a xive_os_cam_decode() helper, Cédric Le Goater, 2019/07/31