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Re: [Qemu-ppc] [PATCH] ppc/pnv: Introduce PowerNV machines with fixed CP
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH] ppc/pnv: Introduce PowerNV machines with fixed CPU models |
Date: |
Thu, 25 Jul 2019 13:27:23 +1000 |
User-agent: |
Mutt/1.12.0 (2019-05-25) |
On Wed, Jul 24, 2019 at 11:32:00AM +0200, Cédric Le Goater wrote:
> On 23/07/2019 08:37, David Gibson wrote:
> > On Tue, Jul 23, 2019 at 08:00:27AM +0200, Cédric Le Goater wrote:
> >> On 23/07/2019 03:38, David Gibson wrote:
> >>> On Mon, Jul 22, 2019 at 08:23:47PM +0200, Cédric Le Goater wrote:
> >>>> Make the current "powernv" machine an abstract type and derive from it
> >>>> new machines with specific CPU models: power8, power8e, power8nvl,
> >>>> power9.
> >>>>
> >>>> The "powernv" machine is now an alias on the "powernv9" machine.
> >>>>
> >>>> Signed-off-by: Cédric Le Goater <address@hidden>
> >>>
> >>> Ah, sorry, I wasn't clear here. I don't think we need a different
> >>> machine type for every cpu model, I just think we should have powernv8
> >>> and powernv9. POWER8E and POWER8NVL don't significantly change the
> >>> system design (IIUC) so they can still be done with "-machine powernv8
> >>> -cpu POWER8E" or whatever. I expect the same will be true for POWER9'
> >>> when that comes along
> >>
> >> I understand but I am afraid we will to have one machine per CPU family
> >> because POWER8E and POWER8NVL already have their own PnvChip :
> >>
> >> DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8,
> >> pnv_chip_power8_class_init),
> >> DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E,
> >> pnv_chip_power8e_class_init),
> >> DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
> >> pnv_chip_power8nvl_class_init),
> >
> > Hrm. Is there an actual reason we need different chip classes for
> > these?
> The POWER8 (8E, 8, 8NVL) chips differ by the core :
>
> target/ppc/cpu-models.h: CPU_POWERPC_POWER8E_BASE = 0x004B0000,
> target/ppc/cpu-models.h: CPU_POWERPC_POWER8_BASE = 0x004D0000,
> target/ppc/cpu-models.h: CPU_POWERPC_POWER8NVL_BASE = 0x004C0000,
>
> The chip model is different :
>
> k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
> k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
> k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
>
> The chiplets are different also. NVL has a NPU and a different LPC bus which
> is modeled. There are different number of PHBs.
Ah, ok. That seems like enough reason.
>
> > Even if there is, I don't see an inherent reason that implies separate
> > machine classes as well.
>
> I will see if we can have a single powernv8 machine.
>
> C.
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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