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From: | Ivan Warren |
Subject: | [Qemu-ppc] [PATCH] Allow bit 15 to be set to 1 on slbmfee and slbmfev as per, Power ISA 3.02B Book III |
Date: | Thu, 18 Jul 2019 11:05:36 +0200 |
User-agent: | Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
Would that work ?Allow Bit 15 in slbmfee and slbmfev per Power ISA 3.0 Book III - Original patch from "Zhuowei Zhang" (no known email address)
Signed-off-by: Ivan Warren<address@hidden> target/ppc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4a5de28036..85f8b147ba 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c@@ -7064,8 +7064,8 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT_64B),GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), +GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001E0001, PPC_SEGMENT_64B), +GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001E0001, PPC_SEGMENT_64B), GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
#endif GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), -- Le 7/18/2019 à 10:33 AM, Greg Kurz a écrit :
Hi Ivan, When it comes to submit patches, there are some rules to follow. Please have a look at this page: https://wiki.qemu.org/Contribute/SubmitAPatch On Tue, 16 Jul 2019 09:35:43 +0200 Ivan Warren <address@hidden> wrote:-------- Message transféré -------- Sujet : TCG - Allow bit 15 to 1 for slbmfee and slbmfev Date : Tue, 16 Jul 2019 09:12:52 +0200 De : Ivan Warren <address@hidden> Pour : address@hidden All, Submitting proposal :Formal greeting is nice :), but we don't want that to go into 'git log'. The two paragraphs below are what we want to keep as a changelog.Per Power ISA 3.02B Book III at pages 1029 and 1030, bit 15 of the slbmfee and slbmfev instructions is now assigned to an implementation specific bit and is no longer reserved - meaning it can be set to 1 but can probably be safely ignored. 2.07B still indicates bit 15 is reserved but some non Linux Operating system's debugger DO set this bit to 1 (so it was probably valid yet not documented for Power 7/8). Therefore I propose :Here should be your Signed-off-by: tag instead, followed by '---', the diffstat and finally the patch (git format-patch does this for free).diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4a5de28036..85f8b147ba 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7064,8 +7064,8 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT_64B), GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), +GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001E0001, PPC_SEGMENT_64B), +GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001E0001, PPC_SEGMENT_64B), GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), #endif GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), PS : This patch is not mine, but gleaned from "Zhuowei Zhang" (no known e-mail address). I am just attempting to have it validated.Well, the best validation is to have it merged upstream... hence the need to post it in a proper format :) If this is someone else's patch then it should have his/her Signed-off-by: tag... Can you get in touch with that person ?
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