qemu-ppc
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-ppc] Power9 VRMA emulation


From: David Gibson
Subject: Re: [Qemu-ppc] Power9 VRMA emulation
Date: Thu, 6 Jun 2019 13:33:01 +1000
User-agent: Mutt/1.11.4 (2019-03-13)

On Thu, May 23, 2019 at 09:57:18AM +0530, Amol Surati wrote:
> On Thu, May 23, 2019 at 09:32:06AM +1000, David Gibson wrote:
> > On Sat, May 18, 2019 at 10:47:22AM +0530, Amol Surati wrote:
> > > Hello again,
> > > 
> > > 
> > > A bit of testing was carried out.
> > > 
> > > 
> > > 
> > > As it is now, qemu raises a HISI without consulting the VRMA SLB and the
> > > partitions page table.
> > > 
> > > This is the message it prints for when a (non-zero LPIDR) partition was 
> > > made
> > > to run under VRMA (for an arbitrary instruction address 0x8ee8):
> > > 
> > > "Raise exception at 0000000000008ee8 => 00000046 (8000000)"
> > > The error code 8000000 is SRR1_PROTFAULT.
> > > 
> > > 
> > > 
> > > After allowing LPCR_VPM0 as a valid bit for POWERPC_MMU_3_00, and setting
> > > it to 1, the above test was repeated. This is the output:
> > > 
> > > htab_base 0000000000000000 htab_mask 00000000000007ff hash 
> > > 0003fffffffffff7
> > > 0 htab=0000000000000000/00000000000007ff vsid=0000000001ffffff
> > > ptem=4001ffffff000001 hash=0003fffffffffff7
> > > 1 htab=0000000000000000/00000000000007ff vsid=0000000001ffffff
> > > api=4001ffffff000003 hash=fffc000000000008
> > > Raise exception at 0000000000008ee8 => 00000046 (40000000)
> > > 
> > > The error code 40000000 is SRR1_NOPTE. That code and qemu's attempt to
> > > search in the page table for the partition, correspond with the comment
> > > in the ISA that HISI is to be raised only when (1) VPM is ON and (2)
> > > conditions exist which warrant raising a ISI/DSI.
> > > 
> > > IIURC, the conditions which warrant raising a storage interrupt are those
> > > which correspond to failure in translating VA to RA (i.e. failure in
> > > finding a valid PTE, assuming TLB was empty).
> > > 
> > > 
> > > 
> > > 
> > > QEMU seems to ignore that bit of ISA and raises the HISI (in the above
> > > test) without checking the page table. Instead of removing LPCR_VPM0 bit
> > > for POWERPC_MMU_3_00, qemu should consider that bit as 1 for all
> > > purposes except for the display purpose.
> > > 
> > > Does that make sense, or am I misinterpreting the ISA?
> > 
> > Which version of qemu are you using?  I quite recently merged a bunch
> > of patches from Suraj which make a number of fixes to TCG's HV mode
> > implementation.
> 
> The version is the latest available at qemu's official upstream
> repository - "QEMU emulator version 4.0.50 (v4.0.0-718-ga4f667b671)" at
> the moment.
> 
> I also checked (but did not build and run) dgibson/master,
> dgibson/ppc-for-4.1 and legoater/powernv-4.1 for how these repos treat
> VPM0 and VRMA.

Ah, sorry, I got confused.  Suraj posted a series of patches improving
emulation of the bare metal MMU and I thought I'd applied them, but in
fact they had some problems and I didn't.  When Suraj has time I
expect he'll rework then and we'll eventually include them/

> Although all four repos know about VPM0 being deprecated in P9, they
> treat VPM0 as OFF for the P9 mmu. The reason could be that VRMA isn't
> supported on P9 yet, as hinted by the comments found here:
> 
> "Re-enable RMLS on POWER9 for virtual hypervisors".
> https://patchwork.kernel.org/patch/10815527/
> 
> 
> Thank you,
> Amol
> 
> > 
> 
> 

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

Attachment: signature.asc
Description: PGP signature


reply via email to

[Prev in Thread] Current Thread [Next in Thread]