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[Qemu-ppc] [PULL 34/60] target/ppc: introduce single fpr_offset() functi
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 34/60] target/ppc: introduce single fpr_offset() function |
Date: |
Sun, 10 Mar 2019 19:26:37 +1100 |
From: Mark Cave-Ayland <address@hidden>
Instead of having multiple copies of the offset calculation logic, move it to a
single fpr_offset() function.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu.h | 7 ++++++-
target/ppc/translate.c | 4 ++--
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 81763d72f9..15e053becd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2563,9 +2563,14 @@ static inline bool lsw_reg_in_range(int start, int
nregs, int rx)
}
/* Accessors for FP, VMX and VSX registers */
+static inline int fpr_offset(int i)
+{
+ return offsetof(CPUPPCState, vsr[i].u64[0]);
+}
+
static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
{
- return &env->vsr[i].u64[0];
+ return (uint64_t *)((uintptr_t)env + fpr_offset(i));
}
static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b156be4d98..668d4cf75a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6677,12 +6677,12 @@ GEN_TM_PRIV_NOOP(trechkpt);
static inline void get_fpr(TCGv_i64 dst, int regno)
{
- tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0]));
+ tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
}
static inline void set_fpr(int regno, TCGv_i64 src)
{
- tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0]));
+ tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
}
static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
--
2.20.1
- [Qemu-ppc] [PULL 32/60] ppc/pnv: psi: add a reset handler, (continued)
- [Qemu-ppc] [PULL 32/60] ppc/pnv: psi: add a reset handler, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 24/60] ppc/pnv: export the xive_router_notify() routine, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 30/60] ppc/pnv: fix logging primitives using Ox, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 23/60] ppc/xive: export the TIMA memory accessors, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 28/60] ppc/pnv: introduce a new pic_print_info() operation to the chip model, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 27/60] ppc/pnv: introduce a new dt_populate() operation to the chip model, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 40/60] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 37/60] target/ppc: introduce avr_full_offset() function, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 26/60] ppc/pnv: add a XIVE interrupt controller model for POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 35/60] target/ppc: introduce single vsrl_offset() function, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 34/60] target/ppc: introduce single fpr_offset() function,
David Gibson <=
- [Qemu-ppc] [PULL 39/60] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 43/60] ppc/pnv: add a PSI bridge class model, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 33/60] spapr_iommu: Do not replay mappings from just created DMA window, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 42/60] mac_newworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 38/60] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 56/60] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 36/60] target/ppc: move Vsr* macros from internal.h to cpu.h, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 58/60] target/ppc: Optimize xviexpdp() using deposit_i64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 50/60] ppc/pnv: add a OCC model class, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 45/60] ppc/pnv: lpc: fix OPB address ranges, David Gibson, 2019/03/10