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Re: [Qemu-ppc] [PATCH v2 08/15] ppc/pnv: add a OCC model class
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v2 08/15] ppc/pnv: add a OCC model class |
Date: |
Fri, 8 Mar 2019 11:29:13 +1100 |
User-agent: |
Mutt/1.11.3 (2019-02-01) |
On Thu, Mar 07, 2019 at 11:35:41PM +0100, Cédric Le Goater wrote:
> To ease the introduction of the OCC model for POWER9, provide a new
> class attributes to define XSCOM operations per CPU family and a PSI
> IRQ number.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
> Reviewed-by: David Gibson <address@hidden>
Applied, thanks.
> ---
>
> Changes in v2:
>
> - new attributes to define XSCOM operations per CPU family and a PSI
> IRQ number.
>
> include/hw/ppc/pnv_occ.h | 15 +++++++++++
> hw/ppc/pnv.c | 2 +-
> hw/ppc/pnv_occ.c | 55 +++++++++++++++++++++++++++-------------
> 3 files changed, 54 insertions(+), 18 deletions(-)
>
> diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
> index 82f299dc76ff..dab5a05f8e99 100644
> --- a/include/hw/ppc/pnv_occ.h
> +++ b/include/hw/ppc/pnv_occ.h
> @@ -23,6 +23,8 @@
>
> #define TYPE_PNV_OCC "pnv-occ"
> #define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC)
> +#define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8"
> +#define PNV8_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV8_OCC)
>
> typedef struct PnvOCC {
> DeviceState xd;
> @@ -35,4 +37,17 @@ typedef struct PnvOCC {
> MemoryRegion xscom_regs;
> } PnvOCC;
>
> +#define PNV_OCC_CLASS(klass) \
> + OBJECT_CLASS_CHECK(PnvOCCClass, (klass), TYPE_PNV_OCC)
> +#define PNV_OCC_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(PnvOCCClass, (obj), TYPE_PNV_OCC)
> +
> +typedef struct PnvOCCClass {
> + DeviceClass parent_class;
> +
> + int xscom_size;
> + const MemoryRegionOps *xscom_ops;
> + int psi_irq;
> +} PnvOCCClass;
> +
> #endif /* _PPC_PNV_OCC_H */
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 918fae057b5c..6ae9ce679505 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -790,7 +790,7 @@ static void pnv_chip_power8_instance_init(Object *obj)
> OBJECT(&chip8->psi), &error_abort);
>
> object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
> - TYPE_PNV_OCC, &error_abort, NULL);
> + TYPE_PNV8_OCC, &error_abort, NULL);
> object_property_add_const_link(OBJECT(&chip8->occ), "psi",
> OBJECT(&chip8->psi), &error_abort);
> }
> diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> index 04880f26d612..ea725647c988 100644
> --- a/hw/ppc/pnv_occ.c
> +++ b/hw/ppc/pnv_occ.c
> @@ -34,15 +34,17 @@
> static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
> {
> bool irq_state;
> + PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
>
> val &= 0xffff000000000000ull;
>
> occ->occmisc = val;
> irq_state = !!(val >> 63);
> - pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state);
> + pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
> }
>
> -static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned size)
> +static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
> + unsigned size)
> {
> PnvOCC *occ = PNV_OCC(opaque);
> uint32_t offset = addr >> 3;
> @@ -54,13 +56,13 @@ static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr
> addr, unsigned size)
> break;
> default:
> qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> - HWADDR_PRIx "\n", addr);
> + HWADDR_PRIx "\n", addr >> 3);
> }
> return val;
> }
>
> -static void pnv_occ_xscom_write(void *opaque, hwaddr addr,
> - uint64_t val, unsigned size)
> +static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> {
> PnvOCC *occ = PNV_OCC(opaque);
> uint32_t offset = addr >> 3;
> @@ -77,13 +79,13 @@ static void pnv_occ_xscom_write(void *opaque, hwaddr addr,
> break;
> default:
> qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> - HWADDR_PRIx "\n", addr);
> + HWADDR_PRIx "\n", addr >> 3);
> }
> }
>
> -static const MemoryRegionOps pnv_occ_xscom_ops = {
> - .read = pnv_occ_xscom_read,
> - .write = pnv_occ_xscom_write,
> +static const MemoryRegionOps pnv_occ_power8_xscom_ops = {
> + .read = pnv_occ_power8_xscom_read,
> + .write = pnv_occ_power8_xscom_write,
> .valid.min_access_size = 8,
> .valid.max_access_size = 8,
> .impl.min_access_size = 8,
> @@ -91,27 +93,42 @@ static const MemoryRegionOps pnv_occ_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> +static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
> +{
> + PnvOCCClass *poc = PNV_OCC_CLASS(klass);
> +
> + poc->xscom_size = PNV_XSCOM_OCC_SIZE;
> + poc->xscom_ops = &pnv_occ_power8_xscom_ops;
> + poc->psi_irq = PSIHB_IRQ_OCC;
> +}
> +
> +static const TypeInfo pnv_occ_power8_type_info = {
> + .name = TYPE_PNV8_OCC,
> + .parent = TYPE_PNV_OCC,
> + .instance_size = sizeof(PnvOCC),
> + .class_init = pnv_occ_power8_class_init,
> +};
>
> static void pnv_occ_realize(DeviceState *dev, Error **errp)
> {
> PnvOCC *occ = PNV_OCC(dev);
> + PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
> Object *obj;
> - Error *error = NULL;
> + Error *local_err = NULL;
>
> occ->occmisc = 0;
>
> - /* get PSI object from chip */
> - obj = object_property_get_link(OBJECT(dev), "psi", &error);
> + obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
> if (!obj) {
> - error_setg(errp, "%s: required link 'psi' not found: %s",
> - __func__, error_get_pretty(error));
> + error_propagate(errp, local_err);
> + error_prepend(errp, "required link 'psi' not found: ");
> return;
> }
> occ->psi = PNV_PSI(obj);
>
> /* XScom region for OCC registers */
> - pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_ops,
> - occ, "xscom-occ", PNV_XSCOM_OCC_SIZE);
> + pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
> + occ, "xscom-occ", poc->xscom_size);
> }
>
> static void pnv_occ_class_init(ObjectClass *klass, void *data)
> @@ -119,6 +136,7 @@ static void pnv_occ_class_init(ObjectClass *klass, void
> *data)
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> dc->realize = pnv_occ_realize;
> + dc->desc = "PowerNV OCC Controller";
> }
>
> static const TypeInfo pnv_occ_type_info = {
> @@ -126,11 +144,14 @@ static const TypeInfo pnv_occ_type_info = {
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(PnvOCC),
> .class_init = pnv_occ_class_init,
> + .class_size = sizeof(PnvOCCClass),
> + .abstract = true,
> };
>
> static void pnv_occ_register_types(void)
> {
> type_register_static(&pnv_occ_type_info);
> + type_register_static(&pnv_occ_power8_type_info);
> }
>
> -type_init(pnv_occ_register_types)
> +type_init(pnv_occ_register_types);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-ppc] [PATCH v2 05/15] ppc/pnv: add a 'dt_isa_nodename' to the chip, (continued)
[Qemu-ppc] [PATCH v2 07/15] ppc/pnv: add SerIRQ routing registers, Cédric Le Goater, 2019/03/07
[Qemu-ppc] [PATCH v2 01/15] ppc/pnv: add a PSI bridge class model, Cédric Le Goater, 2019/03/07
[Qemu-ppc] [PATCH v2 15/15] target/ppc: add HV support for POWER9, Cédric Le Goater, 2019/03/07
[Qemu-ppc] [PATCH v2 08/15] ppc/pnv: add a OCC model class, Cédric Le Goater, 2019/03/07
- Re: [Qemu-ppc] [PATCH v2 08/15] ppc/pnv: add a OCC model class,
David Gibson <=
[Qemu-ppc] [PATCH v2 06/15] ppc/pnv: add a LPC Controller model for POWER9, Cédric Le Goater, 2019/03/07
[Qemu-ppc] [PATCH v2 04/15] ppc/pnv: add a LPC Controller class model, Cédric Le Goater, 2019/03/07