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Re: [Qemu-ppc] [PATCH 20/27] ppc/pnv: add a OCC model class
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 20/27] ppc/pnv: add a OCC model class |
Date: |
Thu, 7 Mar 2019 15:26:42 +1100 |
User-agent: |
Mutt/1.11.3 (2019-02-01) |
On Wed, Mar 06, 2019 at 09:50:25AM +0100, Cédric Le Goater wrote:
> It will ease the introduction of the OCC model for POWER9.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
> ---
> include/hw/ppc/pnv_occ.h | 14 ++++++++++++++
> hw/ppc/pnv.c | 2 +-
> hw/ppc/pnv_occ.c | 23 ++++++++++++++++++++---
> 3 files changed, 35 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
> index 82f299dc76ff..ce2631e21f5e 100644
> --- a/include/hw/ppc/pnv_occ.h
> +++ b/include/hw/ppc/pnv_occ.h
> @@ -23,6 +23,9 @@
>
> #define TYPE_PNV_OCC "pnv-occ"
> #define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC)
> +#define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8"
> +#define PNV8_OCC(obj) \
> + OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV8_OCC)
>
> typedef struct PnvOCC {
> DeviceState xd;
> @@ -35,4 +38,15 @@ typedef struct PnvOCC {
> MemoryRegion xscom_regs;
> } PnvOCC;
>
> +#define PNV_OCC_CLASS(klass) \
> + OBJECT_CLASS_CHECK(PnvOCCClass, (klass), TYPE_PNV_OCC)
> +#define PNV_OCC_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(PnvOCCClass, (obj), TYPE_PNV_OCC)
> +
> +typedef struct PnvOCCClass {
> + DeviceClass parent_class;
> +
> + int xscom_size;
> +} PnvOCCClass;
> +
> #endif /* _PPC_PNV_OCC_H */
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 895be470af67..81ab53899dbc 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -808,7 +808,7 @@ static void pnv_chip_power8_instance_init(Object *obj)
> OBJECT(&chip8->psi), &error_abort);
>
> object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
> - TYPE_PNV_OCC, &error_abort, NULL);
> + TYPE_PNV8_OCC, &error_abort, NULL);
> object_property_add_const_link(OBJECT(&chip8->occ), "psi",
> OBJECT(&chip8->psi), &error_abort);
> }
> diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> index 04880f26d612..a210f44926aa 100644
> --- a/hw/ppc/pnv_occ.c
> +++ b/hw/ppc/pnv_occ.c
> @@ -54,7 +54,7 @@ static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr
> addr, unsigned size)
> break;
> default:
> qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> - HWADDR_PRIx "\n", addr);
> + HWADDR_PRIx "\n", addr >> 3);
> }
> return val;
> }
> @@ -77,7 +77,7 @@ static void pnv_occ_xscom_write(void *opaque, hwaddr addr,
> break;
> default:
> qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> - HWADDR_PRIx "\n", addr);
> + HWADDR_PRIx "\n", addr >> 3);
> }
> }
>
> @@ -95,6 +95,7 @@ static const MemoryRegionOps pnv_occ_xscom_ops = {
> static void pnv_occ_realize(DeviceState *dev, Error **errp)
> {
> PnvOCC *occ = PNV_OCC(dev);
> + PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
> Object *obj;
> Error *error = NULL;
>
> @@ -111,9 +112,23 @@ static void pnv_occ_realize(DeviceState *dev, Error
> **errp)
>
> /* XScom region for OCC registers */
> pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_ops,
> - occ, "xscom-occ", PNV_XSCOM_OCC_SIZE);
> + occ, "xscom-occ", poc->xscom_size);
> }
>
> +static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
> +{
> + PnvOCCClass *poc = PNV_OCC_CLASS(klass);
> +
> + poc->xscom_size = PNV_XSCOM_OCC_SIZE;
> +}
> +
> +static const TypeInfo pnv_occ_power8_type_info = {
> + .name = TYPE_PNV8_OCC,
> + .parent = TYPE_PNV_OCC,
> + .instance_size = sizeof(PnvOCC),
> + .class_init = pnv_occ_power8_class_init,
> +};
> +
> static void pnv_occ_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -124,6 +139,7 @@ static void pnv_occ_class_init(ObjectClass *klass, void
> *data)
> static const TypeInfo pnv_occ_type_info = {
> .name = TYPE_PNV_OCC,
> .parent = TYPE_DEVICE,
> + .abstract = true,
> .instance_size = sizeof(PnvOCC),
> .class_init = pnv_occ_class_init,
> };
> @@ -131,6 +147,7 @@ static const TypeInfo pnv_occ_type_info = {
> static void pnv_occ_register_types(void)
> {
> type_register_static(&pnv_occ_type_info);
> + type_register_static(&pnv_occ_power8_type_info);
> }
>
> type_init(pnv_occ_register_types)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH 22/27] ppc/pnv: extend XSCOM core support for POWER9, (continued)
- [Qemu-ppc] [PATCH 22/27] ppc/pnv: extend XSCOM core support for POWER9, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 16/27] ppc/pnv: lpc: fix OPB address ranges, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 14/27] ppc/pnv: add a PSI bridge model class, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 13/27] ppc/pnv: psi: add a reset handler, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 20/27] ppc/pnv: add a OCC model class, Cédric Le Goater, 2019/03/06
- Re: [Qemu-ppc] [PATCH 20/27] ppc/pnv: add a OCC model class,
David Gibson <=
- [Qemu-ppc] [PATCH 18/27] ppc/pnv: add a LPC Controller model for POWER9, Cédric Le Goater, 2019/03/06
[Qemu-ppc] [PATCH 08/27] ppc/pnv: introduce a new pic_print_info() operation to the chip model, Cédric Le Goater, 2019/03/06
[Qemu-ppc] [PATCH 26/27] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, Cédric Le Goater, 2019/03/06
[Qemu-ppc] [PATCH 17/27] ppc/pnv: add a LPC Controller model class, Cédric Le Goater, 2019/03/06