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[Qemu-ppc] [PATCH 19/27] ppc/pnv: add SerIRQ routing registers
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH 19/27] ppc/pnv: add SerIRQ routing registers |
Date: |
Wed, 6 Mar 2019 09:50:24 +0100 |
This is just a simple reminder that SerIRQ routing should be
addressed.
Signed-off-by: Cédric Le Goater <address@hidden>
---
include/hw/ppc/pnv_lpc.h | 2 ++
hw/ppc/pnv_lpc.c | 14 ++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index 24fe23f0f63b..ede7802f3420 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -57,6 +57,8 @@ typedef struct PnvLpcController {
MemoryRegion opb_master_regs;
/* OPB Master LS registers */
+ uint32_t opb_irq_route0;
+ uint32_t opb_irq_route1;
uint32_t opb_irq_stat;
uint32_t opb_irq_mask;
uint32_t opb_irq_pol;
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 6df694e0abc1..641e2046db92 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -39,6 +39,8 @@ enum {
};
/* OPB Master LS registers */
+#define OPB_MASTER_LS_ROUTE0 0x8
+#define OPB_MASTER_LS_ROUTE1 0xC
#define OPB_MASTER_LS_IRQ_STAT 0x50
#define OPB_MASTER_IRQ_LPC 0x00000800
#define OPB_MASTER_LS_IRQ_MASK 0x54
@@ -521,6 +523,12 @@ static uint64_t opb_master_read(void *opaque, hwaddr addr,
unsigned size)
uint64_t val = 0xfffffffffffffffful;
switch (addr) {
+ case OPB_MASTER_LS_ROUTE0: /* TODO */
+ val = lpc->opb_irq_route0;
+ break;
+ case OPB_MASTER_LS_ROUTE1: /* TODO */
+ val = lpc->opb_irq_route1;
+ break;
case OPB_MASTER_LS_IRQ_STAT:
val = lpc->opb_irq_stat;
break;
@@ -547,6 +555,12 @@ static void opb_master_write(void *opaque, hwaddr addr,
PnvLpcController *lpc = opaque;
switch (addr) {
+ case OPB_MASTER_LS_ROUTE0: /* TODO */
+ lpc->opb_irq_route0 = val;
+ break;
+ case OPB_MASTER_LS_ROUTE1: /* TODO */
+ lpc->opb_irq_route1 = val;
+ break;
case OPB_MASTER_LS_IRQ_STAT:
lpc->opb_irq_stat &= ~val;
pnv_lpc_eval_irqs(lpc);
--
2.20.1
- [Qemu-ppc] [PATCH 10/27] ppc/xive: Make XIVE generate the proper interrupt types, (continued)
[Qemu-ppc] [PATCH 09/27] ppc/xive: activate HV support, Cédric Le Goater, 2019/03/06
[Qemu-ppc] [PATCH 19/27] ppc/pnv: add SerIRQ routing registers,
Cédric Le Goater <=
[Qemu-ppc] [PATCH 21/27] ppc/pnv: add a OCC model for POWER9, Cédric Le Goater, 2019/03/06
[Qemu-ppc] [PATCH 06/27] ppc/pnv: add a XIVE interrupt controller model for POWER9, Cédric Le Goater, 2019/03/06
[Qemu-ppc] [PATCH 01/27] ppc/xive: hardwire the Physical CAM line of the thread context, Cédric Le Goater, 2019/03/06
[Qemu-ppc] [PATCH 25/27] ppc/pnv: add more dummy XSCOM addresses, Cédric Le Goater, 2019/03/06
[Qemu-ppc] [PATCH 23/27] ppc/pnv: POWER9 XSCOM quad support, Cédric Le Goater, 2019/03/06
[Qemu-ppc] [PATCH 24/27] ppc/pnv: activate XSCOM tests for POWER9, Cédric Le Goater, 2019/03/06