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[Qemu-ppc] [PULL 10/43] ppc: fix crash during branch stepping
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 10/43] ppc: fix crash during branch stepping |
Date: |
Tue, 19 Feb 2019 01:30:16 +1100 |
From: Roman Kapl <address@hidden>
The PPC BRANCH exception could bubble up, but this is an QEMU internal exception
and QEMU then crased. Instead it should trigger TRACE exception, according to
PPC 2.07 book. It could happen only when using branch stepping, which is not
commonly used.
Change gen_prep_dbgex do do trigger TRACE. The excp, argument is now removed,
since the type of exception can be inferred from the singlestep_enabled flags.
removed the guards around gen_exception, since they are unnecessary.
Fixes: 0e3bf48909 ("ppc: add DBCR based debugging").
Signed-off-by: Roman Kapl <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 37 +++++++++++++++----------------------
1 file changed, 15 insertions(+), 22 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5429ceb1ab..d5f29d3536 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -287,26 +287,22 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t
excp,
ctx->exception = (excp);
}
-/* Translates the EXCP_TRACE/BRANCH exceptions used on most PowerPCs to
- * EXCP_DEBUG, if we are running on cores using the debug enable bit (e.g.
- * BookE).
+/*
+ * Tells the caller what is the appropriate exception to generate and prepares
+ * SPR registers for this exception.
+ *
+ * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
+ * POWERPC_EXCP_DEBUG (on BookE).
*/
-static uint32_t gen_prep_dbgex(DisasContext *ctx, uint32_t excp)
+static uint32_t gen_prep_dbgex(DisasContext *ctx)
{
- if ((ctx->singlestep_enabled & CPU_SINGLE_STEP)
- && (excp == POWERPC_EXCP_BRANCH)) {
- /* Trace excpt. has priority */
- excp = POWERPC_EXCP_TRACE;
- }
if (ctx->flags & POWERPC_FLAG_DE) {
target_ulong dbsr = 0;
- switch (excp) {
- case POWERPC_EXCP_TRACE:
+ if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
dbsr = DBCR0_ICMP;
- break;
- case POWERPC_EXCP_BRANCH:
+ } else {
+ /* Must have been branch */
dbsr = DBCR0_BRT;
- break;
}
TCGv t0 = tcg_temp_new();
gen_load_spr(t0, SPR_BOOKE_DBSR);
@@ -315,7 +311,7 @@ static uint32_t gen_prep_dbgex(DisasContext *ctx, uint32_t
excp)
tcg_temp_free(t0);
return POWERPC_EXCP_DEBUG;
} else {
- return excp;
+ return POWERPC_EXCP_TRACE;
}
}
@@ -3652,10 +3648,8 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
if (sse & GDBSTUB_SINGLE_STEP) {
gen_debug_exception(ctx);
} else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
- uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_BRANCH);
- if (excp != POWERPC_EXCP_NONE) {
- gen_exception(ctx, excp);
- }
+ uint32_t excp = gen_prep_dbgex(ctx);
+ gen_exception(ctx, excp);
}
tcg_gen_exit_tb(NULL, 0);
} else {
@@ -7790,9 +7784,8 @@ static void ppc_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
ctx->exception != POWERPC_SYSCALL &&
ctx->exception != POWERPC_EXCP_TRAP &&
ctx->exception != POWERPC_EXCP_BRANCH)) {
- uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_TRACE);
- if (excp != POWERPC_EXCP_NONE)
- gen_exception_nip(ctx, excp, ctx->base.pc_next);
+ uint32_t excp = gen_prep_dbgex(ctx);
+ gen_exception_nip(ctx, excp, ctx->base.pc_next);
}
if (tcg_check_temp_count()) {
--
2.20.1
- [Qemu-ppc] [PULL 00/43] ppc-for-4.0 queue 20190219, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 01/43] hw/ppc/prep: Drop useless inclusion of "hw/i386/pc.h", David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 05/43] spapr_pci: Fix interrupt leak in rtas_ibm_change_msi() error path, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 02/43] spapr: Rename xics to intc in interrupt controller agnostic code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 08/43] mac_newworld: change default NIC to sungem for mac99 machine, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 04/43] target/ppc: Fix msync to do what hardware does, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 07/43] spapr: Disallow unsupported kernel-irqchip settings, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 03/43] target/ppc: Enable reporting of SPRs to GDB, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 06/43] cuda: decrease time delay before raising VIA SR interrupt and remove fast path, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 10/43] ppc: fix crash during branch stepping,
David Gibson <=
- [Qemu-ppc] [PULL 09/43] target/ppc: Remove some #if 0'ed code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 11/43] xive: Only set source type for LSIs, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 13/43] target/ppc: Disable ISA 2.06 PM instructions on POWER9, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 16/43] spapr/irq: remove the XICS offset adjustment, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 17/43] xics: Explicitely call KVM ICP methods from the common code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 19/43] xics: Handle KVM ICP realize from the common code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 12/43] qdev: pass an Object * to qbus_set_hotplug_handler(), David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 15/43] spapr/irq: add an 'nr_irq' parameter to initialize the backend., David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 14/43] spapr: fix out of bounds write in spapr_populate_drmem_v2, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 23/43] xics: Handle KVM ICS reset from the "simple" ICS code, David Gibson, 2019/02/18