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[Qemu-ppc] [PULL 13/29] target/ppc: replace AVR* macros with Vsr* macros
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 13/29] target/ppc: replace AVR* macros with Vsr* macros |
Date: |
Wed, 9 Jan 2019 09:45:44 +1100 |
From: Mark Cave-Ayland <address@hidden>
Now that the VMX and VSR register sets have been combined, the same macros can
be used to access both AVR and VSR field members.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/int_helper.c | 30 +++++++++++++-----------------
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 9d715be25c..598731d47a 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -391,13 +391,9 @@ target_ulong helper_602_mfrom(target_ulong arg)
#if defined(HOST_WORDS_BIGENDIAN)
#define HI_IDX 0
#define LO_IDX 1
-#define AVRB(i) u8[i]
-#define AVRW(i) u32[i]
#else
#define HI_IDX 1
#define LO_IDX 0
-#define AVRB(i) u8[15-(i)]
-#define AVRW(i) u32[3-(i)]
#endif
#if defined(HOST_WORDS_BIGENDIAN)
@@ -3277,11 +3273,11 @@ void helper_vcipher(ppc_avr_t *r, ppc_avr_t *a,
ppc_avr_t *b)
int i;
VECTOR_FOR_INORDER_I(i, u32) {
- result.AVRW(i) = b->AVRW(i) ^
- (AES_Te0[a->AVRB(AES_shifts[4*i + 0])] ^
- AES_Te1[a->AVRB(AES_shifts[4*i + 1])] ^
- AES_Te2[a->AVRB(AES_shifts[4*i + 2])] ^
- AES_Te3[a->AVRB(AES_shifts[4*i + 3])]);
+ result.VsrW(i) = b->VsrW(i) ^
+ (AES_Te0[a->VsrB(AES_shifts[4 * i + 0])] ^
+ AES_Te1[a->VsrB(AES_shifts[4 * i + 1])] ^
+ AES_Te2[a->VsrB(AES_shifts[4 * i + 2])] ^
+ AES_Te3[a->VsrB(AES_shifts[4 * i + 3])]);
}
*r = result;
}
@@ -3292,7 +3288,7 @@ void helper_vcipherlast(ppc_avr_t *r, ppc_avr_t *a,
ppc_avr_t *b)
int i;
VECTOR_FOR_INORDER_I(i, u8) {
- result.AVRB(i) = b->AVRB(i) ^ (AES_sbox[a->AVRB(AES_shifts[i])]);
+ result.VsrB(i) = b->VsrB(i) ^ (AES_sbox[a->VsrB(AES_shifts[i])]);
}
*r = result;
}
@@ -3305,15 +3301,15 @@ void helper_vncipher(ppc_avr_t *r, ppc_avr_t *a,
ppc_avr_t *b)
ppc_avr_t tmp;
VECTOR_FOR_INORDER_I(i, u8) {
- tmp.AVRB(i) = b->AVRB(i) ^ AES_isbox[a->AVRB(AES_ishifts[i])];
+ tmp.VsrB(i) = b->VsrB(i) ^ AES_isbox[a->VsrB(AES_ishifts[i])];
}
VECTOR_FOR_INORDER_I(i, u32) {
- r->AVRW(i) =
- AES_imc[tmp.AVRB(4*i + 0)][0] ^
- AES_imc[tmp.AVRB(4*i + 1)][1] ^
- AES_imc[tmp.AVRB(4*i + 2)][2] ^
- AES_imc[tmp.AVRB(4*i + 3)][3];
+ r->VsrW(i) =
+ AES_imc[tmp.VsrB(4 * i + 0)][0] ^
+ AES_imc[tmp.VsrB(4 * i + 1)][1] ^
+ AES_imc[tmp.VsrB(4 * i + 2)][2] ^
+ AES_imc[tmp.VsrB(4 * i + 3)][3];
}
}
@@ -3323,7 +3319,7 @@ void helper_vncipherlast(ppc_avr_t *r, ppc_avr_t *a,
ppc_avr_t *b)
int i;
VECTOR_FOR_INORDER_I(i, u8) {
- result.AVRB(i) = b->AVRB(i) ^ (AES_isbox[a->AVRB(AES_ishifts[i])]);
+ result.VsrB(i) = b->VsrB(i) ^ (AES_isbox[a->VsrB(AES_ishifts[i])]);
}
*r = result;
}
--
2.20.1
- [Qemu-ppc] [PULL 05/29] target/ppc: fix typo in SIMM5 extraction helper, (continued)
- [Qemu-ppc] [PULL 05/29] target/ppc: fix typo in SIMM5 extraction helper, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 02/29] ppc/spapr: Receive and store device tree blob from SLOF, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 06/29] target/ppc: switch EXTRACT_HELPER macros over to use sextract32/extract32, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 08/29] target/ppc: introduce get_avr64() and set_avr64() helpers for VMX register access, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 03/29] ppc4xx: Disable debug logging by default, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 10/29] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 14/29] MAINTAINERS: Add some missing ppc-related files, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 16/29] spapr: move spapr_create_phb() to core machine code, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 11/29] target/ppc: merge ppc_vsr_t and ppc_avr_t union types, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 18/29] spapr_pci: Define SPAPR_MAX_PHBS in hw/pci-host/spapr.h, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 13/29] target/ppc: replace AVR* macros with Vsr* macros,
David Gibson <=
- [Qemu-ppc] [PULL 15/29] MAINTAINERS: add qemu_vga.ndrv file entry for Mac machines, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 09/29] target/ppc: introduce get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() helpers for VSR register access, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 17/29] pci: allow cleanup/unregistration of PCI root buses, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 07/29] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 12/29] target/ppc: move FP and VMX registers into aligned vsr register array, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 27/29] ppc/xics: allow ICSState to have an offset 0, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 21/29] ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 19/29] spapr/xive: simplify the sPAPR IRQ qirq method for XIVE, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 20/29] spapr: modify the prototype of the cpu_intc_create() method, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 28/29] spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS, David Gibson, 2019/01/08