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[Qemu-ppc] [PATCH v5 1/9] target/ppc: fix typo in SIMM5 extraction helpe
From: |
Mark Cave-Ayland |
Subject: |
[Qemu-ppc] [PATCH v5 1/9] target/ppc: fix typo in SIMM5 extraction helper |
Date: |
Wed, 2 Jan 2019 09:14:15 +0000 |
As the macro name suggests, the argument should be signed and not unsigned.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/ppc/internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index a9bcadff42..8b35863549 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -124,7 +124,7 @@ EXTRACT_SHELPER(SIMM, 0, 16);
/* 16 bits unsigned immediate value */
EXTRACT_HELPER(UIMM, 0, 16);
/* 5 bits signed immediate value */
-EXTRACT_HELPER(SIMM5, 16, 5);
+EXTRACT_SHELPER(SIMM5, 16, 5);
/* 5 bits signed immediate value */
EXTRACT_HELPER(UIMM5, 16, 5);
/* 4 bits unsigned immediate value */
--
2.11.0
- [Qemu-ppc] [PATCH v5 0/9] target/ppc: prepare for conversion to TCG vector operations, Mark Cave-Ayland, 2019/01/02
- [Qemu-ppc] [PATCH v5 1/9] target/ppc: fix typo in SIMM5 extraction helper,
Mark Cave-Ayland <=
- [Qemu-ppc] [PATCH v5 2/9] target/ppc: switch EXTRACT_HELPER macros over to use sextract32/extract32, Mark Cave-Ayland, 2019/01/02
- [Qemu-ppc] [PATCH v5 4/9] target/ppc: introduce get_avr64() and set_avr64() helpers for VMX register access, Mark Cave-Ayland, 2019/01/02
- [Qemu-ppc] [PATCH v5 3/9] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access, Mark Cave-Ayland, 2019/01/02
- [Qemu-ppc] [PATCH v5 6/9] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env, Mark Cave-Ayland, 2019/01/02
- [Qemu-ppc] [PATCH v5 7/9] target/ppc: merge ppc_vsr_t and ppc_avr_t union types, Mark Cave-Ayland, 2019/01/02
- [Qemu-ppc] [PATCH v5 9/9] target/ppc: replace AVR* macros with Vsr* macros, Mark Cave-Ayland, 2019/01/02
- [Qemu-ppc] [PATCH v5 5/9] target/ppc: introduce get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() helpers for VSR register access, Mark Cave-Ayland, 2019/01/02
- [Qemu-ppc] [PATCH v5 8/9] target/ppc: move FP and VMX registers into aligned vsr register array, Mark Cave-Ayland, 2019/01/02
- Re: [Qemu-ppc] [PATCH v5 0/9] target/ppc: prepare for conversion to TCG vector operations, David Gibson, 2019/01/02