[Qemu-ppc] [PATCH v3 0/1] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge

[Cédric Le Goater]

This is a model of the PCIe Host Bridge (PHB3) controller found on a
Power8 processor. The Power8 processor comes in different flavors:
Venice, Murano, Naple, each having a different number of PHBs. Multi
chip is supported, each chip adding its set of PHB3 controllers.

There is no default device layout and PCI devices should be added to
the machine using command line options such as :

  -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
  -netdev 
bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0

  -device megasas,id=scsi0,bus=pcie.1,addr=0x0
  -drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
  -device 
scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2

Git tree available here for testing, based on David's branch:

        https://github.com/legoater/qemu/tree/phb3-3.0

Thanks,

C.

Changes since v2 :

 - kept user creatable PHB3 for later.
 - machine: the default number of PHBs is set to 3 per chip.
 - refreshed the PnvPHB3 object hierarchy with PCIe objects
 - introduced a static PCIe Root Port object under the PHB3 host
   bridge object
 - cleanup the register definitions to fit skiboot current ones
 - introduced a phb3_error() helper routine
 - fixed mask in pnv_phb3_config_write()
 - reworked init and realize routine of PnvPHB3
 - removed the creation of a default PCI bridge under the Root Port
 - simplified the PnvPHB3 properties using the DEFINE_PROP_UINT32 macros
 - MSI: fixed a resend error when P|Q was set
 
What did not change since v2 :

 - the MMIO ops are still the same. The controller has many registers,
   more or less 150, and the current model works well enough not to
   pollute the read/write ops.

Changes since v1 :

 - removed duplication of macros for the register definitions
 - fixed multi chip support
 - introduced a chip class attribute to create all possible PHB3
   devices
 - introduced property handlers to check the validity of the phb index
   and the chip id
 - explored user creatable PHB3 devices


Benjamin Herrenschmidt (1):
  ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge

 default-configs/ppc64-softmmu.mak   |    1 +
 include/hw/pci-host/pnv_phb3.h      |  171 ++++
 include/hw/pci-host/pnv_phb3_regs.h |  432 ++++++++++
 include/hw/ppc/pnv.h                |   22 +
 include/hw/ppc/pnv_xscom.h          |    9 +
 include/hw/ppc/xics.h               |    1 +
 hw/intc/xics.c                      |    2 +-
 hw/pci-host/pnv_phb3.c              | 1146 +++++++++++++++++++++++++++
 hw/pci-host/pnv_phb3_msi.c          |  318 ++++++++
 hw/pci-host/pnv_phb3_pbcq.c         |  347 ++++++++
 hw/ppc/pnv.c                        |   75 +-
 hw/ppc/pnv_xscom.c                  |    6 +-
 hw/pci-host/Makefile.objs           |    1 +
 13 files changed, 2526 insertions(+), 5 deletions(-)
 create mode 100644 include/hw/pci-host/pnv_phb3.h
 create mode 100644 include/hw/pci-host/pnv_phb3_regs.h
 create mode 100644 hw/pci-host/pnv_phb3.c
 create mode 100644 hw/pci-host/pnv_phb3_msi.c
 create mode 100644 hw/pci-host/pnv_phb3_pbcq.c

-- 
2.17.1