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[Qemu-ppc] [PULL 24/35] fpu_helper.c: fix setting FPSCR[FI] bit
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 24/35] fpu_helper.c: fix setting FPSCR[FI] bit |
Date: |
Tue, 3 Jul 2018 15:57:53 +1000 |
From: John Arbuckle <address@hidden>
The FPSCR[FI] bit indicates if the last floating point instruction had a result
that was rounded. Each consecutive floating point instruction is suppose to set
this bit to the correct value. What currently happens is this bit is not set as
often as it should be. I have verified that this is the behavior of a real
PowerPC 950. This patch fixes that problem by deciding to set this bit after
each floating point instruction.
https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-environments-for-32-e3087633.html
Page 63 in table 2-4 is where the description of this bit can be found.
Signed-off-by: John Arbuckle <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/fpu_helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 7714bfe0f9..8675d931b6 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -274,6 +274,7 @@ static inline void float_inexact_excp(CPUPPCState *env)
{
CPUState *cs = CPU(ppc_env_get_cpu(env));
+ env->fpscr |= 1 << FPSCR_FI;
env->fpscr |= 1 << FPSCR_XX;
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
@@ -533,6 +534,7 @@ static void do_float_check_status(CPUPPCState *env,
uintptr_t raddr)
{
CPUState *cs = CPU(ppc_env_get_cpu(env));
int status = get_float_exception_flags(&env->fp_status);
+ bool inexact_happened = false;
if (status & float_flag_divbyzero) {
float_zero_divide_excp(env, raddr);
@@ -542,6 +544,12 @@ static void do_float_check_status(CPUPPCState *env,
uintptr_t raddr)
float_underflow_excp(env);
} else if (status & float_flag_inexact) {
float_inexact_excp(env);
+ inexact_happened = true;
+ }
+
+ /* if the inexact flag was not set */
+ if (inexact_happened == false) {
+ env->fpscr &= ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */
}
if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
--
2.17.1
- [Qemu-ppc] [PULL 26/35] ppc4xx_i2c: Rewrite to model hardware more closely, (continued)
- [Qemu-ppc] [PULL 26/35] ppc4xx_i2c: Rewrite to model hardware more closely, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 14/35] target/ppc: Use atomic cmpxchg for STQCX, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 17/35] target/ppc: Split out gen_load_locked, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 13/35] target/ppc: Use atomic store for STQ, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 25/35] hw/ppc: Give sam46ex its own config option, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 18/35] target/ppc: Split out gen_ld_atomic, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 12/35] target/ppc: Use atomic load for LQ and LQARX, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 31/35] target/ppc/kvm: don't pass cpu to kvm_get_smmu_info(), David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 15/35] target/ppc: Remove POWERPC_EXCP_STCX, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 29/35] ppc440_uc: Basic emulation of PPC440 DMA controller, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 24/35] fpu_helper.c: fix setting FPSCR[FI] bit,
David Gibson <=
- [Qemu-ppc] [PULL 34/35] target/ppc: Relax reserved bitmask of indexed store instructions, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 30/35] target/ppc/kvm: get rid of kvm_get_fallback_smmu_info(), David Gibson, 2018/07/03
- Re: [Qemu-ppc] [PULL 00/35] ppc-for-3.0 queue 20180703, Peter Maydell, 2018/07/03