[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PATCH 21/23] target/ppc: Add ppc_hash64_filter_pagesizes()
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PATCH 21/23] target/ppc: Add ppc_hash64_filter_pagesizes() |
Date: |
Fri, 22 Jun 2018 14:24:35 +1000 |
The paravirtualized PAPR platform sometimes needs to restrict the guest to
using only some of the page sizes actually supported by the host's MMU.
At the moment this is handled in KVM specific code, but for consistency we
want to apply the same limitations to all accelerators.
This makes a start on this by providing a helper function in the cpu code
to allow platform code to remove some of the cpu's page size definitions
via a caller supplied callback.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
---
target/ppc/mmu-hash64.c | 59 +++++++++++++++++++++++++++++++++++++++++
target/ppc/mmu-hash64.h | 3 +++
2 files changed, 62 insertions(+)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index aa200cba4c..276d9015e7 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1166,3 +1166,62 @@ const PPCHash64Options ppc_hash64_opts_POWER7 = {
},
}
};
+
+void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
+ bool (*cb)(void *, uint32_t, uint32_t),
+ void *opaque)
+{
+ PPCHash64Options *opts = cpu->hash64_opts;
+ int i;
+ int n = 0;
+ bool ci_largepage = false;
+
+ assert(opts);
+
+ n = 0;
+ for (i = 0; i < ARRAY_SIZE(opts->sps); i++) {
+ PPCHash64SegmentPageSizes *sps = &opts->sps[i];
+ int j;
+ int m = 0;
+
+ assert(n <= i);
+
+ if (!sps->page_shift) {
+ break;
+ }
+
+ for (j = 0; j < ARRAY_SIZE(sps->enc); j++) {
+ PPCHash64PageSize *ps = &sps->enc[j];
+
+ assert(m <= j);
+ if (!ps->page_shift) {
+ break;
+ }
+
+ if (cb(opaque, sps->page_shift, ps->page_shift)) {
+ if (ps->page_shift >= 16) {
+ ci_largepage = true;
+ }
+ sps->enc[m++] = *ps;
+ }
+ }
+
+ /* Clear rest of the row */
+ for (j = m; j < ARRAY_SIZE(sps->enc); j++) {
+ memset(&sps->enc[j], 0, sizeof(sps->enc[j]));
+ }
+
+ if (m) {
+ n++;
+ }
+ }
+
+ /* Clear the rest of the table */
+ for (i = n; i < ARRAY_SIZE(opts->sps); i++) {
+ memset(&opts->sps[i], 0, sizeof(opts->sps[i]));
+ }
+
+ if (!ci_largepage) {
+ opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
+ }
+}
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 53dcec5b93..f11efc9cbc 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -20,6 +20,9 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
void ppc_hash64_init(PowerPCCPU *cpu);
void ppc_hash64_finalize(PowerPCCPU *cpu);
+void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
+ bool (*cb)(void *, uint32_t, uint32_t),
+ void *opaque);
#endif
/*
--
2.17.1
- [Qemu-ppc] [PATCH 22/23] spapr: Limit available pagesizes to provide a consistent guest environment, (continued)
- [Qemu-ppc] [PATCH 22/23] spapr: Limit available pagesizes to provide a consistent guest environment, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 17/23] target/ppc: Add missing opcode for icbt on PPC440, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 14/23] sm501: Fix hardware cursor color conversion, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 04/23] spapr_cpu_core: migrate VPA related state, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 08/23] spapr: Compute effective capability values earlier, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 20/23] spapr: Use maximum page size capability to simplify memory backend checking, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 16/23] ppc4xx_i2c: Implement directcntl register, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 05/23] ppc/pnv: introduce Pnv8Chip and Pnv9Chip models, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 09/23] spapr: Add cpu_apply hook to capabilities, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 10/23] target/ppc: Add kvmppc_hpt_needs_host_contiguous_pages() helper, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 21/23] target/ppc: Add ppc_hash64_filter_pagesizes(),
David Gibson <=
- [Qemu-ppc] [PATCH 12/23] spapr: remove unused spapr_irq routines, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 07/23] target/ppc: Allow cpu compatiblity checks based on type, not instance, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 19/23] spapr: Maximum (HPT) pagesize property, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 23/23] spapr: Don't rewrite mmu capabilities in KVM mode, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 15/23] ppc4xx_i2c: Remove unimplemented sdata and intr registers, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 13/23] fpu_helper.c: fix helper_fpscr_clrbit() function, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 11/23] spapr: split the IRQ allocation sequence, David Gibson, 2018/06/22
- [Qemu-ppc] [PATCH 18/23] pseries: Update SLOF firmware image to qemu-slof-20180621, David Gibson, 2018/06/22
- Re: [Qemu-ppc] [PATCH 01/23] ppc/pnv: introduce a new intc_create() operation to the chip model, Greg Kurz, 2018/06/22