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[Qemu-ppc] [PATCH 1/3] mos6522: only clear the shift register interrupt
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From: |
Mark Cave-Ayland |
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Subject: |
[Qemu-ppc] [PATCH 1/3] mos6522: only clear the shift register interrupt upon write |
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Date: |
Wed, 13 Jun 2018 09:30:13 +0100 |
According to the 6522 datasheet the shift register (SR) interrupt flag is
cleared upon write with no mention of any other interrupt flags.
Signed-off-by: Mark Cave-Ayland <address@hidden>
---
hw/misc/mos6522.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 44eb306cf1..ad5041d8c0 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -241,7 +241,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned
size)
break;
case VIA_REG_SR:
val = s->sr;
- s->ifr &= ~(SR_INT | CB1_INT | CB2_INT);
+ s->ifr &= ~SR_INT;
mos6522_update_irq(s);
break;
case VIA_REG_ACR:
--
2.11.0