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[Qemu-ppc] [PATCH v4 25/28] spapr: fix XICS migration
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v4 25/28] spapr: fix XICS migration |
Date: |
Thu, 7 Jun 2018 17:50:00 +0200 |
Extend the sPAPR IRQ backend with a new handler to handle XICS
post_load() specificities.
Signed-off-by: Cédric Le Goater <address@hidden>
---
include/hw/ppc/spapr_irq.h | 1 +
hw/ppc/spapr.c | 9 ++-------
hw/ppc/spapr_irq.c | 24 ++++++++++++++++++++++++
3 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
index 85829928a9c4..1ca35ffc13cd 100644
--- a/include/hw/ppc/spapr_irq.h
+++ b/include/hw/ppc/spapr_irq.h
@@ -47,6 +47,7 @@ typedef struct sPAPRIrq {
void *fdt, uint32_t phandle);
Object *(*cpu_intc_create)(sPAPRMachineState *spapr, Object *cpu,
Error **errp);
+ void (*post_load)(sPAPRMachineState *spapr);
} sPAPRIrq;
extern sPAPRIrq spapr_irq_legacy;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 2774b53f169e..025d5af84def 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1689,6 +1689,7 @@ static int spapr_pre_load(void *opaque)
static int spapr_post_load(void *opaque, int version_id)
{
sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
+ sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
int err = 0;
err = spapr_caps_post_migration(spapr);
@@ -1696,13 +1697,7 @@ static int spapr_post_load(void *opaque, int version_id)
return err;
}
- if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
- CPUState *cs;
- CPU_FOREACH(cs) {
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- icp_resend(ICP(cpu->intc));
- }
- }
+ smc->irq->post_load(spapr);
/* In earlier versions, there was no separate qdev for the PAPR
* RTC, so the RTC offset was stored directly in sPAPREnvironment.
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index a5d89c6ac55f..5f445e17d125 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -254,6 +254,17 @@ static Object
*spapr_irq_cpu_intc_create_legacy(sPAPRMachineState *spapr,
return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp);
}
+static void spapr_irq_post_load_legacy(sPAPRMachineState *spapr)
+{
+ if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
+ CPUState *cs;
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ icp_resend(ICP(cpu->intc));
+ }
+ }
+}
+
sPAPRIrq spapr_irq_legacy = {
.nr_irqs = XICS_IRQS_SPAPR,
.ov5 = 0x0, /* XICS only */
@@ -266,6 +277,7 @@ sPAPRIrq spapr_irq_legacy = {
.print_info = spapr_irq_print_info_legacy,
.dt_populate = spapr_irq_dt_populate_legacy,
.cpu_intc_create = spapr_irq_cpu_intc_create_legacy,
+ .post_load = spapr_irq_post_load_legacy,
};
/*
@@ -487,6 +499,11 @@ static Object
*spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
return spapr_irq_cpu_intc_create_legacy(spapr, cpu, errp);
}
+static void spapr_irq_post_load_xics(sPAPRMachineState *spapr)
+{
+ spapr_irq_post_load_legacy(spapr);
+}
+
/*
* XICS IRQ number space
*
@@ -534,6 +551,7 @@ sPAPRIrq spapr_irq_xics = {
.print_info = spapr_irq_print_info_xics,
.dt_populate = spapr_irq_dt_populate_xics,
.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
+ .post_load = spapr_irq_post_load_xics,
};
/*
@@ -716,6 +734,11 @@ static Object
*spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
XIVE_ROUTER(spapr->xive), errp);
}
+static void spapr_irq_post_load_xive(sPAPRMachineState *spapr)
+{
+ ;
+}
+
/*
* XIVE IRQ number space
*
@@ -765,6 +788,7 @@ sPAPRIrq spapr_irq_xive = {
.print_info = spapr_irq_print_info_xive,
.dt_populate = spapr_irq_dt_populate_xive,
.cpu_intc_create = spapr_irq_cpu_intc_create_xive,
+ .post_load = spapr_irq_post_load_xive,
};
/*
--
2.13.6
- [Qemu-ppc] [PATCH v4 15/28] spapr: initialize VSMT before initializing the IRQ backend, (continued)
- [Qemu-ppc] [PATCH v4 15/28] spapr: initialize VSMT before initializing the IRQ backend, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 16/28] spapr: introdude a new machine IRQ backend for XIVE, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 17/28] spapr: add hcalls support for the XIVE exploitation interrupt mode, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 18/28] spapr: add device tree support for the XIVE exploitation mode, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 19/28] spapr: allocate the interrupt thread context under the CPU core, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 20/28] spapr: introduce a 'pseries-3.0-xive' QEMU machine, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 21/28] spapr: add classes for the XIVE models, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 22/28] target/ppc/kvm: add Linux KVM definitions for XIVE, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 23/28] spapr/xive: add common realize routine for KVM, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 24/28] spapr/xive: add KVM support, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 25/28] spapr: fix XICS migration,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v4 26/28] pnv: add a physical mapping array describing MMIO ranges in each chip, Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 27/28] ppc: externalize ppc_get_vcpu_by_pir(), Cédric Le Goater, 2018/06/07
- [Qemu-ppc] [PATCH v4 28/28] ppc/pnv: add XIVE support, Cédric Le Goater, 2018/06/07