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[Qemu-ppc] [PATCH v2 7/8] sm501: Do not clear read only bits when writin
From: |
BALATON Zoltan |
Subject: |
[Qemu-ppc] [PATCH v2 7/8] sm501: Do not clear read only bits when writing register |
Date: |
Wed, 06 Jun 2018 15:31:48 +0200 |
When writing a register that has read only bits besides reserved bits
we have to avoid changing read only bits that may have non zero
default values.
Signed-off-by: BALATON Zoltan <address@hidden>
---
hw/display/sm501.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index e47be99..7ec1434 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -836,10 +836,10 @@ static void sm501_system_config_write(void *opaque,
hwaddr addr,
switch (addr) {
case SM501_SYSTEM_CONTROL:
- s->system_control = value & 0xE300B8F7;
+ s->system_control |= value & 0xEF00B8F7;
break;
case SM501_MISC_CONTROL:
- s->misc_control = value & 0xFF7FFF20;
+ s->misc_control |= value & 0xFF7FFF10;
break;
case SM501_GPIO31_0_CONTROL:
s->gpio_31_0_control = value;
@@ -853,7 +853,7 @@ static void sm501_system_config_write(void *opaque, hwaddr
addr,
s->dram_control |= value & 0x7FFFFFC3;
break;
case SM501_ARBTRTN_CONTROL:
- s->arbitration_control = value & 0x37777777;
+ s->arbitration_control = value & 0x37777777;
break;
case SM501_IRQ_MASK:
s->irq_mask = value;
--
2.7.6
- Re: [Qemu-ppc] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, (continued)
[Qemu-ppc] [PATCH v2 4/8] ppc4xx_i2c: Rewrite to model hardware more closely, BALATON Zoltan, 2018/06/06
[Qemu-ppc] [PATCH v2 2/8] ppc4xx_i2c: Move register state to private struct and remove unimplemented sdata and intr registers, BALATON Zoltan, 2018/06/06
[Qemu-ppc] [PATCH v2 8/8] sm501: Implement i2c part for reading monitor EDID, BALATON Zoltan, 2018/06/06
[Qemu-ppc] [PATCH v2 7/8] sm501: Do not clear read only bits when writing register,
BALATON Zoltan <=