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[Qemu-ppc] [PULL 23/49] ppc: Fix size of ppc64 xer register
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 23/49] ppc: Fix size of ppc64 xer register |
Date: |
Fri, 27 Apr 2018 19:21:00 +1000 |
From: Michael Matz <address@hidden>
The normal gdb definition of the XER registers is only 32 bit,
and that's what the current version of power64-core.xml also
says (seems copied from gdb's). But qemu's idea of the XER register
is target_ulong (in CPUPPCState, ppc_gdb_register_len and
ppc_cpu_gdb_read_register)
That mismatch leads to the following message when attaching
with gdb:
Truncated register 32 in remote 'g' packet
(and following on that qemu stops responding). The simple fix is
to say the truth in the .xml file. But the better fix is to
actually make it 32bit on the wire, as old gdbs don't support
XML files for describing registers. Also the XER state in qemu
doesn't seem to use the high 32 bits, so sending it off to gdb
doesn't seem worthwhile.
Signed-off-by: Michael Matz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/gdbstub.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 7a338136a8..b6f6693583 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -37,10 +37,10 @@ static int ppc_gdb_register_len_apple(int n)
case 65+32: /* msr */
case 67+32: /* lr */
case 68+32: /* ctr */
- case 69+32: /* xer */
case 70+32: /* fpscr */
return 8;
case 66+32: /* cr */
+ case 69+32: /* xer */
return 4;
default:
return 0;
@@ -61,6 +61,8 @@ static int ppc_gdb_register_len(int n)
return 8;
case 66:
/* cr */
+ case 69:
+ /* xer */
return 4;
case 64:
/* nip */
@@ -70,8 +72,6 @@ static int ppc_gdb_register_len(int n)
/* lr */
case 68:
/* ctr */
- case 69:
- /* xer */
return sizeof(target_ulong);
case 70:
/* fpscr */
@@ -152,7 +152,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t
*mem_buf, int n)
gdb_get_regl(mem_buf, env->ctr);
break;
case 69:
- gdb_get_regl(mem_buf, env->xer);
+ gdb_get_reg32(mem_buf, env->xer);
break;
case 70:
gdb_get_reg32(mem_buf, env->fpscr);
@@ -208,7 +208,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t
*mem_buf, int n)
gdb_get_reg64(mem_buf, env->ctr);
break;
case 69 + 32:
- gdb_get_reg64(mem_buf, env->xer);
+ gdb_get_reg32(mem_buf, env->xer);
break;
case 70 + 32:
gdb_get_reg64(mem_buf, env->fpscr);
@@ -259,7 +259,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
env->ctr = ldtul_p(mem_buf);
break;
case 69:
- env->xer = ldtul_p(mem_buf);
+ env->xer = ldl_p(mem_buf);
break;
case 70:
/* fpscr */
@@ -309,7 +309,7 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t
*mem_buf, int n)
env->ctr = ldq_p(mem_buf);
break;
case 69 + 32:
- env->xer = ldq_p(mem_buf);
+ env->xer = ldl_p(mem_buf);
break;
case 70 + 32:
/* fpscr */
--
2.14.3
- [Qemu-ppc] [PULL 18/49] uninorth: remove obsolete pci_pmac_init() function, (continued)
- [Qemu-ppc] [PULL 18/49] uninorth: remove obsolete pci_pmac_init() function, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 39/49] target/ppc: Move 1T segment and AMR options to PPCHash64Options, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 37/49] target/ppc: Split page size information into a separate allocation, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 38/49] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 40/49] target/ppc: Fold ci_large_pages flag into PPCHash64Options, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 34/49] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 21/49] uninorth: move PCI IO (ISA) memory region into the uninorth device, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 33/49] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop(), David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 31/49] target/ppc: Standardize instance_init and realize function names, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 42/49] target/ppc: Get rid of POWERPC_MMU_VER() macros, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 23/49] ppc: Fix size of ppc64 xer register,
David Gibson <=
- [Qemu-ppc] [PULL 27/49] Add host_memory_backend_pagesize() helper, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 25/49] spapr: Introduce pseries-2.13 machine type, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 41/49] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 47/49] target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr(), David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 29/49] Revert "spapr: Don't allow memory hotplug to memory less nodes", David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 26/49] Make qemu_mempath_getpagesize() accept NULL, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 44/49] spapr: Add ibm, max-associativity-domains property, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 43/49] target/ppc: Fold slb_nr into PPCHash64Options, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 45/49] ppc: e500: switch E500 based machines to full machine definition, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 32/49] target/ppc: Simplify cpu valid check in ppc_cpu_realize, David Gibson, 2018/04/27