[Qemu-ppc] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines

[Cédric Le Goater]

On a POWER9 processor, the Partition Table is composed of a pair of
doublewords per partition. The first doubleword indicates whether the
partition uses HPT or Radix Trees translation and contains the address
of the host's translation table structure and size.

The first doubleword of the PTCR holds the Hash Page Table base
address for the host when the hash MMU is in use. Add an helper to
retrieve the HPT base address depending on the MMU revision.

Signed-off-by: Cédric Le Goater <address@hidden>
---
 target/ppc/mmu-book3s-v3.h |  5 +++++
 target/ppc/mmu-hash64.c    | 20 ++++++++++++++++++++
 target/ppc/mmu-hash64.h    |  6 ++++--
 3 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index fdf80987d7b2..a7ab580c3140 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -54,6 +54,11 @@ static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
 int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
                               int mmu_idx);
 
+static inline hwaddr ppc64_v3_get_patbe0(PowerPCCPU *cpu)
+{
+    return ldq_phys(CPU(cpu)->as, cpu->env.spr[SPR_PTCR] & PTCR_PATB);
+}
+
 #endif /* TARGET_PPC64 */
 
 #endif /* CONFIG_USER_ONLY */
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index ecea2ae04dd3..fae164d30706 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -290,6 +290,26 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, 
target_ulong rb)
     return rt;
 }
 
+hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
+{
+    CPUPPCState *env = &cpu->env;
+
+    /* We should not reach this routine on sPAPR machines */
+    assert(!cpu->vhyp);
+
+    /* PowerNV machine */
+    if (msr_hv) {
+        if (env->mmu_model & POWERPC_MMU_3_00) {
+            return ppc64_v3_get_patbe0(cpu);
+        } else {
+            return cpu->env.spr[SPR_SDR1];
+        }
+    } else {
+        error_report("PowerNV guest support Unimplemented");
+        exit(1);
+    }
+}
+
 /* Check No-Execute or Guarded Storage */
 static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
                                               ppc_hash_pte64_t pte)
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index a3a0de452b94..daf3ba27e2cc 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -129,12 +129,14 @@ static inline target_ulong 
ppc_hash64_hpte_v_avpn_val(PowerPCCPU *cpu,
         HPTE64_V_AVPN_VAL_3_0(pte0) : HPTE64_V_AVPN_VAL(pte0);
 }
 
+hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu);
+
 static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
 {
     if (cpu->vhyp) {
         return 0;
     }
-    return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
+    return ppc_hash64_hpt_reg(cpu) & SDR_64_HTABORG;
 }
 
 static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
@@ -144,7 +146,7 @@ static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
             PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
         return vhc->hpt_mask(cpu->vhyp);
     }
-    return (1ULL << ((cpu->env.spr[SPR_SDR1] & SDR_64_HTABSIZE) + 18 - 7)) - 1;
+    return (1ULL << ((ppc_hash64_hpt_reg(cpu) & SDR_64_HTABSIZE) + 18 - 7)) - 
1;
 }
 
 struct ppc_hash_pte64 {
-- 
2.13.6