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[Qemu-ppc] [PULL 31/34] ppc: pnv: consolidate type definitions and batch
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 31/34] ppc: pnv: consolidate type definitions and batch register them |
Date: |
Tue, 17 Oct 2017 15:21:49 +1100 |
From: Igor Mammedov <address@hidden>
Use a new DEFINE_TYPES() helper to simplify type registration
Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Acked-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 92 ++++++++++++++++++++++--------------------------------------
1 file changed, 34 insertions(+), 58 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 80c7f62bbc..c35c439d81 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -729,13 +729,6 @@ static void pnv_chip_power8e_class_init(ObjectClass
*klass, void *data)
dc->desc = "PowerNV Chip POWER8E";
}
-static const TypeInfo pnv_chip_power8e_info = {
- .name = TYPE_PNV_CHIP_POWER8E,
- .parent = TYPE_PNV_CHIP,
- .instance_size = sizeof(PnvChip),
- .class_init = pnv_chip_power8e_class_init,
-};
-
static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -750,13 +743,6 @@ static void pnv_chip_power8_class_init(ObjectClass *klass,
void *data)
dc->desc = "PowerNV Chip POWER8";
}
-static const TypeInfo pnv_chip_power8_info = {
- .name = TYPE_PNV_CHIP_POWER8,
- .parent = TYPE_PNV_CHIP,
- .instance_size = sizeof(PnvChip),
- .class_init = pnv_chip_power8_class_init,
-};
-
static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -771,13 +757,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
*klass, void *data)
dc->desc = "PowerNV Chip POWER8NVL";
}
-static const TypeInfo pnv_chip_power8nvl_info = {
- .name = TYPE_PNV_CHIP_POWER8NVL,
- .parent = TYPE_PNV_CHIP,
- .instance_size = sizeof(PnvChip),
- .class_init = pnv_chip_power8nvl_class_init,
-};
-
static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -792,13 +771,6 @@ static void pnv_chip_power9_class_init(ObjectClass *klass,
void *data)
dc->desc = "PowerNV Chip POWER9";
}
-static const TypeInfo pnv_chip_power9_info = {
- .name = TYPE_PNV_CHIP_POWER9,
- .parent = TYPE_PNV_CHIP,
- .instance_size = sizeof(PnvChip),
- .class_init = pnv_chip_power9_class_init,
-};
-
static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
@@ -1000,15 +972,6 @@ static void pnv_chip_class_init(ObjectClass *klass, void
*data)
dc->desc = "PowerNV Chip";
}
-static const TypeInfo pnv_chip_info = {
- .name = TYPE_PNV_CHIP,
- .parent = TYPE_SYS_BUS_DEVICE,
- .class_init = pnv_chip_class_init,
- .instance_init = pnv_chip_init,
- .class_size = sizeof(PnvChipClass),
- .abstract = true,
-};
-
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
PnvMachineState *pnv = POWERNV_MACHINE(xi);
@@ -1144,27 +1107,40 @@ static void powernv_machine_class_init(ObjectClass *oc,
void *data)
powernv_machine_class_props_init(oc);
}
-static const TypeInfo powernv_machine_info = {
- .name = TYPE_POWERNV_MACHINE,
- .parent = TYPE_MACHINE,
- .instance_size = sizeof(PnvMachineState),
- .instance_init = powernv_machine_initfn,
- .class_init = powernv_machine_class_init,
- .interfaces = (InterfaceInfo[]) {
- { TYPE_XICS_FABRIC },
- { TYPE_INTERRUPT_STATS_PROVIDER },
- { },
+#define DEFINE_PNV_CHIP_TYPE(type, class_initfn) \
+ { \
+ .name = type, \
+ .class_init = class_initfn, \
+ .parent = TYPE_PNV_CHIP, \
+ }
+
+static const TypeInfo types[] = {
+ {
+ .name = TYPE_POWERNV_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(PnvMachineState),
+ .instance_init = powernv_machine_initfn,
+ .class_init = powernv_machine_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XICS_FABRIC },
+ { TYPE_INTERRUPT_STATS_PROVIDER },
+ { },
+ },
},
+ {
+ .name = TYPE_PNV_CHIP,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .class_init = pnv_chip_class_init,
+ .instance_init = pnv_chip_init,
+ .instance_size = sizeof(PnvChip),
+ .class_size = sizeof(PnvChipClass),
+ .abstract = true,
+ },
+ DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
+ DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
+ DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
+ DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
+ pnv_chip_power8nvl_class_init),
};
-static void powernv_machine_register_types(void)
-{
- type_register_static(&powernv_machine_info);
- type_register_static(&pnv_chip_info);
- type_register_static(&pnv_chip_power8e_info);
- type_register_static(&pnv_chip_power8_info);
- type_register_static(&pnv_chip_power8nvl_info);
- type_register_static(&pnv_chip_power9_info);
-}
-
-type_init(powernv_machine_register_types)
+DEFINE_TYPES(types)
--
2.13.6
- [Qemu-ppc] [PULL 13/34] ppc: mac_oldworld: use generic cpu_model parsing, (continued)
- [Qemu-ppc] [PULL 13/34] ppc: mac_oldworld: use generic cpu_model parsing, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 09/34] qom: introduce type_register_static_array(), David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 22/34] ppc: spapr: register 'host' core type along with the rest of core types, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 12/34] ppc: mac_newworld: use generic cpu_model parsing, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 16/34] ppc: virtex-ml507: replace cpu_model with cpu_type, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 18/34] ppc: spapr: replace ppc_cpu_parse_features() with cpu_parse_cpu_model(), David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 08/34] hw/ppc/spapr.c: abort unplug_request if previous unplug isn't done, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 19/34] ppc: move '-cpu foo, compat=xxx' parsing into ppc_cpu_parse_featurestr(), David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 33/34] spapr_pci: fail gracefully with non-pseries machine types, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 14/34] ppc: bamboo: use generic cpu_model parsing, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 31/34] ppc: pnv: consolidate type definitions and batch register them,
David Gibson <=
- [Qemu-ppc] [PULL 07/34] target/ppc: Fix carry flag setting for shift algebraic instructions, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 15/34] ppc: replace cpu_model with cpu_type on ref405ep, taihu boards, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 11/34] ppc: mpc8544ds/e500plat: use generic cpu_model parsing, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 24/34] ppc: move ppc_cpu_lookup_alias() before its first user, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 23/34] ppc: spapr: use cpu model names as tcg defaults instead of aliases, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 34/34] spapr_cpu_core: rewrite machine type sanity check, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 28/34] ppc: pnv: drop PnvCoreClass::cpu_oc field, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 29/34] ppc: pnv: define core types statically, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 21/34] ppc: spapr: use cpu type name directly, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 20/34] ppc: spapr: define core types statically, David Gibson, 2017/10/17