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Re: [Qemu-ppc] [PATCH v3 0/6] The series enables Multi-Threaded TCG on P
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v3 0/6] The series enables Multi-Threaded TCG on PPC64 |
Date: |
Mon, 1 May 2017 16:08:02 +1000 |
User-agent: |
Mutt/1.8.0 (2017-02-23) |
On Thu, Apr 27, 2017 at 10:48:18AM +0530, Nikunj A Dadhania wrote:
> Patch 01: Use atomic_cmpxchg in store conditional
> 02: Handle first write to page during atomic operation
> 03: Generate memory barriers for sync/isync and load/store conditional
> 04: Fix CPU unplug in MTTCG
> 05: Enable MTTCG by default on PPC64
> 06: Fixes a bug in PPC where the reservation is reset
> causing atomic operations to never succeed
>
> Patches are based on ppc-for-2.10
Applied to ppc-for-2.10, thanks.
>
> Changelog:
> v2:
> * David found problem related to clang and "make check" that was
> root caused to a tcg bug and the patch is in mainline:
>
> 79b1af9 tcg: Initialize return value after exit_atomic
>
> * Fixed a bug in ppc_cpu_exec_enter(), which was resetting the
> reserve_addr, this should be done in powerpc_excp()
>
> v1:
> * Rewrote store_conditional as suggested by Richard
>
> Bharata B Rao (1):
> cpus: Fix CPU unplug for MTTCG
>
> Nikunj A Dadhania (5):
> target/ppc: Emulate LL/SC using cmpxchg helpers
> cputlb: handle first atomic write to the page
> target/ppc: Generate fence operations
> tcg: enable MTTCG by default for PPC64 on x86
> target/ppc: do not reset reserve_addr in exec_enter
>
> configure | 2 ++
> cpus.c | 6 ++++++
> cputlb.c | 8 +++++++-
> target/ppc/cpu.h | 2 ++
> target/ppc/excp_helper.c | 3 +++
> target/ppc/translate.c | 37 +++++++++++++++++++++++++++++++------
> target/ppc/translate_init.c | 9 ---------
> 7 files changed, 51 insertions(+), 16 deletions(-)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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