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Re: [Qemu-ppc] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instruction
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions |
Date: |
Thu, 24 Nov 2016 12:02:12 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Wed, Nov 23, 2016 at 05:07:18PM +0530, Nikunj A Dadhania wrote:
> From: Avinesh Kumar <address@hidden>
>
> vextublx: Vector Extract Unsigned Byte Left
> vextuhlx: Vector Extract Unsigned Halfword Left
> vextuwlx: Vector Extract Unsigned Word Left
>
> Signed-off-by: Avinesh Kumar <address@hidden>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
So, when I suggested doing these without helpers before, I had
forgotten that the non-byte versions can straddle the word boundary.
Given that the offset is in a register, not the instruction that does
make it complicated.
But, this version also relies on working 128-bit arithmetic, AFAICT
this will just fail to build if CONFIG_INT128 isn't defined. It
really shouldn't be that hard to make a helper that works just in
terms of 64-bit arithmetic - there are only 3 cases (all in the upper
word, all in the lower, and straddling). I'd prefer to see it done
that way, rather than increasing reliance on CONFIG_INT128.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH v1 01/10] target-ppc: Consolidate instruction decode helpers, (continued)
- [Qemu-ppc] [PATCH v1 01/10] target-ppc: Consolidate instruction decode helpers, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 02/10] target-ppc: rename CRF_* defines as CRF_*_BIT, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 04/10] target-ppc: Add xscmpexp[dp, qp] instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 03/10] target-ppc: Fix xscmpodp and xscmpudp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 06/10] target-ppc: implement lxsd and lxssp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 07/10] target-ppc: implement stxsd and stxssp, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 05/10] target-ppc: Add xscmpoqp and xscmpuqp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 08/10] target-ppc: implement lxv/lxvx and stxv/stxvx, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions, Nikunj A Dadhania, 2016/11/23
- Re: [Qemu-ppc] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions,
David Gibson <=
[Qemu-ppc] [PATCH v1 10/10] target-ppc: add vextu[bhw]rx instructions, Nikunj A Dadhania, 2016/11/23
Re: [Qemu-ppc] [PATCH v1 ppc-for-2.9 00/10] POWER9 TCG enablements - part8, David Gibson, 2016/11/23