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[Qemu-ppc] [PATCH v5 13/17] ppc/xics: add a xics_get_cpu_index_by_pir he
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v5 13/17] ppc/xics: add a xics_get_cpu_index_by_pir helper |
Date: |
Sat, 22 Oct 2016 11:46:46 +0200 |
We will need this helper to translate the server number of the XIVE
(which is a PIR) into an ICPState index number (which is a cpu index).
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/intc/xics_native.c | 19 +++++++++++++++++++
include/hw/ppc/xics.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c
index bbdd786aeb50..6318862f53fc 100644
--- a/hw/intc/xics_native.c
+++ b/hw/intc/xics_native.c
@@ -33,6 +33,25 @@
#include <libfdt.h>
+int xics_get_cpu_index_by_pir(XICSState *xics, int pir)
+{
+ int i;
+
+ for (i = 0; i < xics->nr_servers; i++) {
+ ICPState *icp = &xics->ss[i];
+ if (icp->cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(icp->cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (env->spr_cb[SPR_PIR].default_value == pir) {
+ return i;
+ }
+ }
+ }
+
+ return -1;
+}
+
static void xics_native_reset(void *opaque)
{
device_reset(DEVICE(opaque));
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 911cdd5e549f..beb232e616c5 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -214,6 +214,7 @@ void xics_set_nr_servers(XICSState *xics, uint32_t
nr_servers,
/* Internal XICS interfaces */
int xics_get_cpu_index_by_dt_id(int cpu_dt_id);
+int xics_get_cpu_index_by_pir(XICSState *xics, int pir);
void icp_set_cppr(ICPState *icp, uint8_t cppr);
void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
--
2.7.4
- [Qemu-ppc] [PATCH v5 10/17] ppc/pnv: add a ISA bus, (continued)
[Qemu-ppc] [PATCH v5 12/17] ppc/pnv: add a XICS native to each PowerNV chip, Cédric Le Goater, 2016/10/22
[Qemu-ppc] [PATCH v5 13/17] ppc/xics: add a xics_get_cpu_index_by_pir helper,
Cédric Le Goater <=
[Qemu-ppc] [PATCH v5 14/17] ppc/xics: introduce a helper to insert a new ics, Cédric Le Goater, 2016/10/22
[Qemu-ppc] [PATCH v5 15/17] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt, Cédric Le Goater, 2016/10/22