Re: [Qemu-ppc] [RFC 2/4] spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM

[David Gibson]

On Thu, Oct 06, 2016 at 09:21:56AM +0200, Laurent Vivier wrote:
> 
> 
> On 06/10/2016 05:03, David Gibson wrote:
> > Currently the default PCI host bridge for the 'pseries' machine type is
> > constructed with its IO windows in the 1TiB..(1TiB + 64GiB) range in
> > guest memory space.  This means that if > 1TiB of guest RAM is specified,
> > the RAM will collide with the PCI IO windows, causing serious problems.
> > 
> > Problems won't be obvious until guest RAM goes a bit beyond 1TiB, because
> > there's a little unused space at the bottom of the area reserved for PCI,
> > but essentially this means that > 1TiB of RAM has never worked with the
> > pseries machine type.
> > 
> > This patch fixes this by altering the placement of PHBs on large-RAM VMs.
> > Instead of always placing the first PHB at 1TiB, it is placed at the next
> > 1 TiB boundary after the maximum RAM address.
> > 
> > Technically, this changes behaviour in a migration-breaking way for
> > existing machines with > 1TiB maximum memory, but since having > 1 TiB
> > memory was broken anyway, this seems like a reasonable trade-off.
> 
> Perhaps you can add an SPAPR_COMPAT_XX property with PHB0 base to not
> break compatibility? I think spapr without PCI card (only VIO, for
> instance), should work with 1TiB+.

No, it won't because we always create the default PHB even if we don't
actually have any PCI devices.

> On another side, how the SPAPR kernel manages memory?
> Is it possible to add an hole in RAM between 1TiB and 1TiB+64GiB to
> allow the kernel to register the I/O space?

Possible, yes, but I don't really see any advantage to it.

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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