[Qemu-ppc] [PATCH v4 00/20] ppc/pnv: booting the kernel and reaching user space

[Cédric Le Goater]

Hello,

Here is a v4 addressing all the comments from v3 and adding a couple
more models. Most important changes are :

 - a rework of the XSCOM model which now dispatches addresses to the
   memory regions using pcb_addr << 3. 
 - the model for the native Interrupt Presentation Controllers based
   on MMIOS, borrowed from Nikunj v3 patchset, plus some extras to
   support HW CPU ids,
 - a minimal PSI HB (Processor Service Interface Host Bus) model to
   handle the external interrupt, 
 - initial support for the POWER9 LPC controller.


The initial patch provides a minimal platform with some RAM to load
the ROMs : firmware, kernel and initrd. The device tree is built with
what is available at reset time. Then, comes the PnvChip object acting
as a container for other devices required to run a system. The cores
are added to each chip with some restrictions on the number and the
ids. Next is the XSCOM model, the sideband bus which gives controls to
all the units in the POWER8 chip, the LPC controller for the console,
the native interrupt controller and the PSI HB model to handle the
external interrupt.

Last is an initial LPC controller model for the POWER9. We have a
console ! But, more important, it gives us an idea of what changes we
should consider. The LPC controller is a little different for POWER9
as it is accessed through MMIOs but it is not too complex to adapt the
code from POWER8. PSIHB has different XSCOMs addresses, we should be
OK with the current framework. The POWER9 interrupt controller is
another story for later.

The next step is a PHB3 model to include some PCI devices. Nevertheless,
the patchset has now enough support to be usable as a real machine. If
you still feel adventurous, you can grab skiboot and kernel images
here :

  
https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/skiboot.lid
  
https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/zImage.epapr
  
https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/rootfs.cpio.xz

The code is available here (beware this is a wip branch)

   https://github.com/legoater/qemu/commits/powernv-ipmi-2.8

Thanks,

C. 

Benjamin Herrenschmidt (9):
  ppc/pnv: add skeleton PowerNV platform
  ppc/pnv: add a LPC controller
  ppc/xics: Make the ICSState a list
  ppc/xics: Split ICS into ics-base and ics class
  ppc/xics: Add xics to the monitor "info pic" command
  ppc/xics: Add "native" XICS subclass
  ppc/pnv: Add cut down PSI bridge model and hookup external interrupt
  ppc/pnv: Add OCC model stub with interrupt support
  ppc/pnv: Add Naples chip support for LPC interrupts

Cédric Le Goater (11):
  ppc/pnv: add a PnvChip object
  ppc/pnv: add a core mask to PnvChip
  ppc/pnv: add a PIR handler to PnvChip
  ppc/pnv: add a PnvCore object
  ppc/pnv: add XSCOM infrastructure
  ppc/pnv: add XSCOM handlers to PnvCore
  ppc/pnv: add a ISA bus
  ppc/xics: introduce helpers to find an ICP from some (CPU) index
  ppc/xics: introduce a helper to insert a new ics
  ppc/pnv: add a XICS native to each PowerNV chip
  ppc/pnv: add support for POWER9 LPC Controller

 default-configs/ppc64-softmmu.mak |   4 +-
 hmp-commands-info.hx              |   2 +
 hw/intc/Makefile.objs             |   1 +
 hw/intc/trace-events              |  15 +-
 hw/intc/xics.c                    | 337 ++++++++++-----
 hw/intc/xics_kvm.c                |  44 +-
 hw/intc/xics_native.c             | 327 ++++++++++++++
 hw/intc/xics_spapr.c              | 128 +++---
 hw/ppc/Makefile.objs              |   2 +
 hw/ppc/pnv.c                      | 878 ++++++++++++++++++++++++++++++++++++++
 hw/ppc/pnv_core.c                 | 253 +++++++++++
 hw/ppc/pnv_lpc.c                  | 745 ++++++++++++++++++++++++++++++++
 hw/ppc/pnv_occ.c                  | 135 ++++++
 hw/ppc/pnv_psi.c                  | 598 ++++++++++++++++++++++++++
 hw/ppc/pnv_xscom.c                | 262 ++++++++++++
 hw/ppc/ppc.c                      |  14 +
 hw/ppc/spapr_events.c             |   2 +-
 hw/ppc/spapr_pci.c                |   5 +-
 hw/ppc/spapr_vio.c                |   2 +-
 include/hw/ppc/pnv.h              | 164 +++++++
 include/hw/ppc/pnv_core.h         |  50 +++
 include/hw/ppc/pnv_lpc.h          | 107 +++++
 include/hw/ppc/pnv_occ.h          |  38 ++
 include/hw/ppc/pnv_psi.h          |  64 +++
 include/hw/ppc/pnv_xscom.h        |  75 ++++
 include/hw/ppc/ppc.h              |   2 +
 include/hw/ppc/xics.h             |  69 ++-
 monitor.c                         |   4 +
 28 files changed, 4129 insertions(+), 198 deletions(-)
 create mode 100644 hw/intc/xics_native.c
 create mode 100644 hw/ppc/pnv.c
 create mode 100644 hw/ppc/pnv_core.c
 create mode 100644 hw/ppc/pnv_lpc.c
 create mode 100644 hw/ppc/pnv_occ.c
 create mode 100644 hw/ppc/pnv_psi.c
 create mode 100644 hw/ppc/pnv_xscom.c
 create mode 100644 include/hw/ppc/pnv.h
 create mode 100644 include/hw/ppc/pnv_core.h
 create mode 100644 include/hw/ppc/pnv_lpc.h
 create mode 100644 include/hw/ppc/pnv_occ.h
 create mode 100644 include/hw/ppc/pnv_psi.h
 create mode 100644 include/hw/ppc/pnv_xscom.h

-- 
2.7.4