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[Qemu-ppc] [PULL 26/64] ppc: FP exceptions are always precise
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 26/64] ppc: FP exceptions are always precise |
Date: |
Wed, 7 Sep 2016 20:29:05 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
We don't implement imprecise FP exceptions and using store_current
which sets SRR1 to the *previous* instruction never makes sense
for these. So let's be truthful and make them precise, which is
allowed by the architecture.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/excp_helper.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 96c6fd9..02d9e79 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -274,12 +274,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
env->error_code = 0;
return;
}
+
+ /* FP exceptions always have NIP pointing to the faulting
+ * instruction, so always use store_next and claim we are
+ * precise in the MSR.
+ */
msr |= 0x00100000;
- if (msr_fe0 == msr_fe1) {
- goto store_next;
- }
- msr |= 0x00010000;
- break;
+ goto store_next;
case POWERPC_EXCP_INVAL:
LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
msr |= 0x00080000;
--
2.7.4
- [Qemu-ppc] [PULL 03/64] target-ppc: Introduce Power9 family, (continued)
- [Qemu-ppc] [PULL 03/64] target-ppc: Introduce Power9 family, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 04/64] target-ppc: Introduce POWER ISA 3.0 flag, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 07/64] target-ppc: add modulo word operations, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 11/64] target-ppc: add cmpeqb instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 10/64] target-ppc: add cnttzw[.] instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 02/64] hw/ppc: include fdt helper routine in a common file, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 15/64] target-ppc: introduce opc4 for Expanded Opcode, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 12/64] target-ppc: add setb instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 16/64] ppc: Provide basic raise_exception_* functions, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 33/64] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 26/64] ppc: FP exceptions are always precise,
David Gibson <=
- [Qemu-ppc] [PULL 31/64] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 50/64] target-ppc: add vsrv instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 37/64] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 13/64] target-ppc: add maddld instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 41/64] ppc: Don't set access_type on all load/stores on hash64, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 55/64] ppc: Fix macio ESCC legacy mapping, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 44/64] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 27/64] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 39/64] ppc: Speed up dcbz, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 58/64] ppc: Don't generate dead code on unconditional branches, David Gibson, 2016/09/07