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[Qemu-ppc] [PATCH v4 06/15] target-ppc: add modulo dword operations
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v4 06/15] target-ppc: add modulo dword operations |
Date: |
Tue, 26 Jul 2016 17:28:29 +0530 |
Adding following instructions for ISA3.0 support
modud: Modulo Unsigned Dword
modsd: Modulo Signed Dword
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden
---
target-ppc/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 966e848..7c7328f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1221,6 +1221,52 @@ static void glue(gen_, name)(DisasContext *ctx)
\
GEN_INT_ARITH_MODW(moduw, 0x08, 0);
GEN_INT_ARITH_MODW(modsw, 0x18, 1);
+#if defined(TARGET_PPC64)
+static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
+ TCGv arg2, int sign)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_mov_i64(t0, arg1);
+ tcg_gen_mov_i64(t1, arg2);
+ if (sign) {
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+ tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
+ tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
+ tcg_gen_and_i64(t2, t2, t3);
+ tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
+ tcg_gen_or_i64(t2, t2, t3);
+ tcg_gen_movi_i64(t3, 0);
+ tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_rem_i64(ret, t0, t1);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+ } else {
+ TCGv_i64 t2 = tcg_const_i64(1);
+ TCGv_i64 t3 = tcg_const_i64(0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
+ tcg_gen_remu_i64(ret, t0, t1);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+#define GEN_INT_ARITH_MODD(name, opc3, sign) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
+ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
+ sign); \
+}
+
+GEN_INT_ARITH_MODD(modud, 0x08, 0);
+GEN_INT_ARITH_MODD(modsd, 0x18, 1);
+#endif
+
/* mulhw mulhw. */
static void gen_mulhw(DisasContext *ctx)
{
@@ -10303,6 +10349,8 @@ GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE,
PPC2_DIVE_ISA206),
GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
+GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
#undef GEN_INT_ARITH_MUL_HELPER
#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
--
2.7.4
- [Qemu-ppc] [PATCH v4 00/15] POWER9 TCG enablements - part1, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 01/15] target-ppc: Introduce Power9 family, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 02/15] target-ppc: Introduce POWER ISA 3.0 flag, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 03/15] target-ppc: adding addpcis instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 04/15] target-ppc: add cmprb instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 06/15] target-ppc: add modulo dword operations,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v4 05/15] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 10/15] target-ppc: add cnttzw[.] instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 08/15] target-ppc: implement branch-less divd[o][.], Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 15/15] target-ppc: introduce opc4 for Expanded Opcode, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 14/15] target-ppc: add maddhd and maddhdu instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 13/15] target-ppc: add maddld instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 07/15] target-ppc: implement branch-less divw[o][.], Nikunj A Dadhania, 2016/07/26