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[Qemu-ppc] [RFC v2 06/13] target-ppc: add modulo dword operations
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [RFC v2 06/13] target-ppc: add modulo dword operations |
Date: |
Sat, 23 Jul 2016 14:14:43 +0530 |
Adding following instructions for ISA3.0 support
modud: Modulo Unsigned Dword
modsd: Modulo Signed Dword
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/helper.h | 2 ++
target-ppc/int_helper.c | 16 ++++++++++++++++
target-ppc/translate.c | 15 +++++++++++++++
3 files changed, 33 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 76072fd..26a0930 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -45,6 +45,8 @@ DEF_HELPER_FLAGS_2(modsw, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(moduw, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_3(sraw, tl, env, tl, tl)
#if defined(TARGET_PPC64)
+DEF_HELPER_FLAGS_2(modsd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(modud, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 631e0b4..e95572b 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -161,6 +161,22 @@ target_ulong helper_cntlzw(target_ulong t)
}
#if defined(TARGET_PPC64)
+uint64_t helper_modsd(uint64_t rau, uint64_t rbu)
+{
+ int64_t ra = (int64_t)rau;
+ int64_t rb = (int64_t)rbu;
+
+ if ((rb == 0) || (ra == INT32_MIN && rb == -1)) {
+ return 0;
+ }
+ return ra % rb;
+}
+
+uint64_t helper_modud(uint64_t ra, uint64_t rb)
+{
+ return rb ? ra % rb : 0;
+}
+
target_ulong helper_cntlzd(target_ulong t)
{
return clz64(t);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4348efd..38a117c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1192,6 +1192,19 @@ static void glue(gen_, name)(DisasContext *ctx)
\
GEN_INT_ARITH_MODW(moduw, 0x08, 0);
GEN_INT_ARITH_MODW(modsw, 0x18, 1);
+#if defined(TARGET_PPC64)
+#define GEN_INT_ARITH_MODD(name, opc3, sign) \
+ static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
+ cpu_gpr[rA(ctx->opcode)], \
+ cpu_gpr[rB(ctx->opcode)]); \
+}
+
+GEN_INT_ARITH_MODD(modud, 0x08, 0);
+GEN_INT_ARITH_MODD(modsd, 0x18, 1);
+#endif
+
/* mulhw mulhw. */
static void gen_mulhw(DisasContext *ctx)
{
@@ -10274,6 +10287,8 @@ GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE,
PPC2_DIVE_ISA206),
GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
+GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
#undef GEN_INT_ARITH_MUL_HELPER
#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
--
2.7.4
- [Qemu-ppc] [RFC v2 03/13] target-ppc: adding addpcis instruction, (continued)
[Qemu-ppc] [RFC v2 06/13] target-ppc: add modulo dword operations,
Nikunj A Dadhania <=
[Qemu-ppc] [RFC v2 08/13] target-ppc: add cnttzw[.] instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 09/13] target-ppc: add cmpeqb instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 10/13] target-ppc: add setb instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 07/13] target-ppc: add cnttzd[.] instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 11/13] target-ppc: add maddld instruction, Nikunj A Dadhania, 2016/07/23