Re: [Qemu-ppc] [PATCH 0/3] ppc: complete the new HV mode

[Benjamin Herrenschmidt]

On Mon, 2016-06-06 at 17:04 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2016-06-06 at 07:29 +0100, Mark Cave-Ayland wrote:
> > 
> > 
> > The best reproducer is to run from David's ppc-for-2.7 branch with
> > the above patch applied manually and then try booting the following
> > ISOs which now panic on boot with the split I/D MMU mode enabled:
> So at least HelenOS is fixed by this:

Note that Cedric is right, the TLB flush batching isn't done for 32-
bit, and we could do it, it would probably improve performances, but it
needs to be done properly :-) I'll look into it next.

> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -1969,6 +1969,11 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
> target_ulong addr)
>          /* XXX: this case should be optimized,
>           * giving a mask to tlb_flush_page
>           */
> +        /* This is broken, some CPUs invalidate a whole congruence
> +         * class on an even smaller subset of bits and some OSes
> take
> +         * advantage of this. Just blow the whole thing away.
> +         */
> +#if 0
>          tlb_flush_page(cs, addr | (0x0 << 28));
>          tlb_flush_page(cs, addr | (0x1 << 28));
>          tlb_flush_page(cs, addr | (0x2 << 28));
> @@ -1985,6 +1990,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
> target_ulong addr)
>          tlb_flush_page(cs, addr | (0xD << 28));
>          tlb_flush_page(cs, addr | (0xE << 28));
>          tlb_flush_page(cs, addr | (0xF << 28));
> +#else
> +        tlb_flush(cs, 1);
> +#endif
>          break;
>  #if defined(TARGET_PPC64)
>      case POWERPC_MMU_64B:
> 
> I'll check Darwin...
> 
> Cheers,
> Ben.