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[Qemu-ppc] [PULL 38/40] target-ppc: Allow more page sizes for POWER7 & P
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 38/40] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG |
Date: |
Mon, 1 Feb 2016 13:31:06 +1100 |
Now that the TCG and spapr code has been extended to allow (semi-)
arbitrary page encodings in the CPU's 'sps' table, we can add the many
page sizes supported by real POWER7 and POWER8 hardware that we previously
didn't support in TCG.
Signed-off-by: David Gibson <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
---
target-ppc/mmu-hash64.h | 2 ++
target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 34cf975..ab0f86b 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -48,6 +48,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
#define SLB_VSID_4K 0x0000000000000000ULL
#define SLB_VSID_64K 0x0000000000000110ULL
+#define SLB_VSID_16M 0x0000000000000100ULL
+#define SLB_VSID_16G 0x0000000000000120ULL
/*
* Hash page table definitions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4d71a5d..cdd18ac 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8105,6 +8105,36 @@ static Property powerpc_servercpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifdef CONFIG_SOFTMMU
+static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
+ .sps = {
+ {
+ .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 },
+ { .page_shift = 16, .pte_enc = 0x7 },
+ { .page_shift = 24, .pte_enc = 0x38 }, },
+ },
+ {
+ .page_shift = 16, /* 64K */
+ .slb_enc = SLB_VSID_64K,
+ .enc = { { .page_shift = 16, .pte_enc = 0x1 },
+ { .page_shift = 24, .pte_enc = 0x8 }, },
+ },
+ {
+ .page_shift = 24, /* 16M */
+ .slb_enc = SLB_VSID_16M,
+ .enc = { { .page_shift = 24, .pte_enc = 0 }, },
+ },
+ {
+ .page_shift = 34, /* 16G */
+ .slb_enc = SLB_VSID_16G,
+ .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
+ },
+ }
+};
+#endif /* CONFIG_SOFTMMU */
+
static void init_proc_POWER7 (CPUPPCState *env)
{
init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
@@ -8168,6 +8198,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->sps = &POWER7_POWER8_sps;
#endif
pcc->excp_model = POWERPC_EXCP_POWER7;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
@@ -8248,6 +8279,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_07;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->sps = &POWER7_POWER8_sps;
#endif
pcc->excp_model = POWERPC_EXCP_POWER7;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
--
2.5.0
- [Qemu-ppc] [PULL 09/40] spapr: Remove abuse of rtas_ld() in h_client_architecture_support, (continued)
- [Qemu-ppc] [PULL 09/40] spapr: Remove abuse of rtas_ld() in h_client_architecture_support, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 20/40] target-ppc: rename and export maybe_bswap_register(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 13/40] pseries: Clean up error handling in spapr_validate_node_memory(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 04/40] macio: add dma_active to VMStateDescription, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 14/40] pseries: Clean up error handling in spapr_vga_init(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 05/40] mac_dbdma: add DBDMA controller state to VMStateDescription, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 10/40] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 12/40] pseries: Clean up error handling of spapr_cpu_init(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 08/40] spapr: Remove rtas_st_buffer_direct(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 21/40] target-ppc: gdbstub: fix float registers for little-endian guests, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 38/40] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG,
David Gibson <=
- [Qemu-ppc] [PULL 16/40] pseries: Clean up error handling in xics_system_init(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 34/40] target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 26/40] pseries: Allow TCG h_enter to work with hotplugged memory, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 36/40] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 40/40] target-ppc: mcrfs should always update FEX/VX and only clear exception bits, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 19/40] target-ppc: kvm: fix floating point registers sync on little-endian hosts, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 18/40] pseries: Clean up error reporting in htab migration functions, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 33/40] target-ppc: Use actual page size encodings from HPTE, David Gibson, 2016/01/31