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Re: [Qemu-ppc] [PATCH 2/2] target-ppc/fpu_helper: fix FPSCR_FX bit shift
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From: |
David Gibson |
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Subject: |
Re: [Qemu-ppc] [PATCH 2/2] target-ppc/fpu_helper: fix FPSCR_FX bit shift operation |
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Date: |
Mon, 30 Nov 2015 13:32:51 +1100 |
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User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Fri, Nov 20, 2015 at 05:01:48PM +0530, Madhavan Srinivasan wrote:
> Currently in TCG mode, updating floating exception
> summary bit (FPSCR_FX) in fpscr also updates
> the upper 32bits of fpscr with all 1s.
> Modify the bit shift operation statement to use
> 1ULL instead.
>
> Signed-off-by: Madhavan Srinivasan <address@hidden>
Looks good to me, applied to ppc-for-2.5.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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