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[Qemu-ppc] [PATCH 64/77] ppc: Fix writing to AMR/UAMOR
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-ppc] [PATCH 64/77] ppc: Fix writing to AMR/UAMOR |
Date: |
Wed, 11 Nov 2015 11:28:17 +1100 |
The masks weren't chosen nor applied properly. The architecture specifies
that writes to AMR are masked by UAMOR for PR=1, otherwise AMOR for HV=0.
The writes to UAMOR are masked by AMOR for HV=0
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/translate_init.c | 76 +++++++++++++++++++++++++++++++++++----------
1 file changed, 60 insertions(+), 16 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index df24b97..aa9eecf 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -1094,30 +1094,72 @@ static void gen_spr_7xx (CPUPPCState *env)
#ifdef TARGET_PPC64
#ifndef CONFIG_USER_ONLY
-static void spr_read_uamr (DisasContext *ctx, int gprn, int sprn)
+static void spr_write_amr (DisasContext *ctx, int sprn, int gprn)
{
- gen_load_spr(cpu_gpr[gprn], SPR_AMR);
- spr_load_dump_spr(SPR_AMR);
-}
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
-static void spr_write_uamr (DisasContext *ctx, int sprn, int gprn)
-{
- gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
+ /* Note, the HV=1 PR=0 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ if (ctx->pr) {
+ gen_load_spr(t1, SPR_UAMOR);
+ } else {
+ gen_load_spr(t1, SPR_AMOR);
+ }
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_AMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_AMR, t0);
spr_store_dump_spr(SPR_AMR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
}
-static void spr_write_uamr_pr (DisasContext *ctx, int sprn, int gprn)
+static void spr_write_uamor (DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /* Note, the HV=1 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+ /* Build insertion mask into t1 based on context */
+ gen_load_spr(t1, SPR_AMOR);
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
gen_load_spr(t0, SPR_UAMOR);
- tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- gen_store_spr(SPR_AMR, t0);
- spr_store_dump_spr(SPR_AMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_UAMOR, t0);
+ spr_store_dump_spr(SPR_UAMOR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
}
#endif /* CONFIG_USER_ONLY */
-static void gen_spr_amr (CPUPPCState *env)
+static void gen_spr_amr (CPUPPCState *env, bool has_iamr)
{
#ifndef CONFIG_USER_ONLY
/* Virtual Page Class Key protection */
@@ -1125,15 +1167,17 @@ static void gen_spr_amr (CPUPPCState *env)
* userspace accessible, 29 is privileged. So we only need to set
* the kvm ONE_REG id on one of them, we use 29 */
spr_register(env, SPR_UAMR, "UAMR",
- &spr_read_uamr, &spr_write_uamr_pr,
- &spr_read_uamr, &spr_write_uamr,
+ &spr_read_generic, &spr_write_amr,
+ &spr_read_generic, &spr_write_amr,
0);
- spr_register_kvm(env, SPR_AMR, "AMR",
+ spr_register_kvm_hv(env, SPR_AMR, "AMR",
SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_amr,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_AMR, 0);
- spr_register_kvm(env, SPR_UAMOR, "UAMOR",
+ spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_uamor,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_UAMOR, 0);
spr_register_hv(env, SPR_AMOR, "AMOR",
--
2.5.0
- [Qemu-ppc] [PATCH 63/77] ppc: Initialize AMOR in PAPR mode, (continued)
- [Qemu-ppc] [PATCH 63/77] ppc: Initialize AMOR in PAPR mode, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 57/77] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 61/77] ppc: SPURR & PURR are HV writeable and privileged, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 55/77] ppc/pnv+spapr: Add "ibm, pa-features" property to the device-tree, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 56/77] ppc: Fix conditions for delivering external interrupts to a guest, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 54/77] ppc: Fix 64K pages support in full emulation, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 58/77] ppc: Initial HDEC support, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 59/77] ppc: Add placeholder SPRs for DPDES and DHDES on P8, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 62/77] ppc: Add dummy SPR_IC for POWER8, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 60/77] ppc: LPCR is a HV resource, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 64/77] ppc: Fix writing to AMR/UAMOR,
Benjamin Herrenschmidt <=
- [Qemu-ppc] [PATCH 65/77] ppc: Add POWER8 IAMR register, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 67/77] ppc: Add dummy write to VTB, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 66/77] ppc: Add a few more P8 PMU SPRs, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 68/77] ppc: Add dummy POWER8 MPPR register, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 72/77] ppc: A couple more dummy POWER8 Book4 regs, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 77/77] ppc: Fix CFAR updates, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 70/77] ppc: Add dummy CIABR SPR, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 69/77] ppc: Add dummy POWER8 PSPB SPR, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 71/77] ppc: Add dummy ACOP SPR, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 73/77] ppc: Add KVM numbers to some P8 SPRs, Benjamin Herrenschmidt, 2015/11/10