[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-ppc] target-ppc: Fix SRR0 when taking unaligned exceptions
From: |
Alexander Graf |
Subject: |
Re: [Qemu-ppc] target-ppc: Fix SRR0 when taking unaligned exceptions |
Date: |
Wed, 26 Aug 2015 11:44:30 +0200 |
User-agent: |
Mozilla/5.0 (Macintosh; Intel Mac OS X 10.10; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 |
On 02.07.15 06:44, Anton Blanchard wrote:
> We are setting SRR0 to the instruction before the one causing the
> unaligned exception. A quick testcase:
>
> . = 0x100
> .globl _start
> _start:
> /* Cause a 0x600 */
> li 3,0x1
> stwcx. 3,0,3
> 1: b 1b
>
> . = 0x600
> 1: b 1b
>
> Built into something we can load as a BIOS image:
>
> gcc -mbig -c test.S
> ld -EB -Ttext 0x0 -o test test.o
> objcopy -O binary test test.bin
>
> Run with:
>
> qemu-system-ppc64 -nographic -bios test.bin
>
> Shows an incorrect SRR0 (points at the li):
>
> SRR0 0000000000000100
>
> With the patch we get the correct SRR0:
>
> SRR0 0000000000000104
>
> Signed-off-by: Anton Blanchard <address@hidden>
Thanks, applied to ppc-next.
Alex
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- Re: [Qemu-ppc] target-ppc: Fix SRR0 when taking unaligned exceptions,
Alexander Graf <=