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[Qemu-ppc] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar(
From: |
Alexey Kardashevskiy |
Subject: |
[Qemu-ppc] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() for POWER7/8 |
Date: |
Tue, 3 Jun 2014 19:27:51 +1000 |
This makes use of generic gen_spr_book3s_lpar() which registers LPCR SPR.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
target-ppc/translate_init.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 40c8ce1..bc68adb 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7800,13 +7800,9 @@ static void init_proc_POWER7 (CPUPPCState *env)
gen_spr_book3s_common(env);
gen_spr_power5p_common(env);
gen_spr_power6_common(env);
+ gen_spr_book3s_lpar(env);
gen_spr_power6_dbg(env);
gen_spr_amr(env);
- /* Logical partitionning */
- spr_register_kvm(env, SPR_LPCR, "LPCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_LPCR, 0x00000000);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
--
2.0.0
- Re: [Qemu-ppc] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR, (continued)
- [Qemu-ppc] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs, Alexey Kardashevskiy, 2014/06/03
- [Qemu-ppc] [PATCH v4 20/29] target-ppc: Add POWER8's FSCR SPR, Alexey Kardashevskiy, 2014/06/03
- [Qemu-ppc] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper, Alexey Kardashevskiy, 2014/06/03
- [Qemu-ppc] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() for POWER7/8,
Alexey Kardashevskiy <=
- [Qemu-ppc] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR, Alexey Kardashevskiy, 2014/06/03
[Qemu-ppc] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs, Alexey Kardashevskiy, 2014/06/03
[Qemu-ppc] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs, Alexey Kardashevskiy, 2014/06/03