Re: [Qemu-ppc] [PATCH V9 5/5] target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab

[Greg Kurz]

On Tue, 28 Jan 2014 13:30:03 +0530
"Aneesh Kumar K.V" <address@hidden> wrote:
> This support updating htab managed by the hypervisor. Currently we don't
> have any user for this feature. This actually bring the store_hpte
> interface in-line with the load_hpte one. We may want to use this when we
> want to emulate henter hcall in qemu for HV kvm.
> 
> Signed-off-by: Aneesh Kumar K.V <address@hidden>
> ---
>  target-ppc/kvm.c        | 30 ++++++++++++++++++++++++++++++
>  target-ppc/kvm_ppc.h    | 10 ++++++++++
>  target-ppc/mmu-hash64.c | 18 ++++++++++++++++++
>  target-ppc/mmu-hash64.h | 16 ++--------------
>  4 files changed, 60 insertions(+), 14 deletions(-)
> 
> diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
> index eefd78afc004..893b59f99fa3 100644
> --- a/target-ppc/kvm.c
> +++ b/target-ppc/kvm.c
> @@ -1989,3 +1989,33 @@ void kvmppc_hash64_free_pteg(uint64_t token)
>      g_free(htab_buf);
>      return;
>  }
> +
> +void kvmppc_hash64_write_pte(CPUPPCState *env, target_ulong pte_index,
> +                             target_ulong pte0, target_ulong pte1)
> +{
> +    int htab_fd;
> +    struct kvm_get_htab_fd ghf;
> +    struct kvm_get_htab_buf hpte_buf;
> +
> +    ghf.flags = 0;
> +    ghf.start_index = 0;     /* Ignored */
> +    htab_fd = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &ghf);
> +    if (htab_fd < 0) {
> +        goto error_out;
> +    }
> +
> +    hpte_buf.header.n_valid = 1;
> +    hpte_buf.header.n_invalid = 0;
> +    hpte_buf.header.index = pte_index;
> +    hpte_buf.hpte[0] = pte0;
> +    hpte_buf.hpte[1] = pte1;
> +    /*
> +     * Write the hpte entry
> +     */
> +    write(htab_fd, &hpte_buf, sizeof(hpte_buf));

Hmmm... this does not compile for me because of the warn_unused_result
attribute. And BTW, why not checking the return value ?


> +    close(htab_fd);
> +    return;
> +
> +error_out:
> +    return;
> +}
> diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
> index 800e1ad0834f..a65d34571914 100644
> --- a/target-ppc/kvm_ppc.h
> +++ b/target-ppc/kvm_ppc.h
> @@ -47,6 +47,9 @@ int kvmppc_load_htab_chunk(QEMUFile *f, int fd,
> uint32_t index, uint64_t kvmppc_hash64_read_pteg(PowerPCCPU *cpu,
> target_ulong pte_index); void kvmppc_hash64_free_pteg(uint64_t token);
> 
> +void kvmppc_hash64_write_pte(CPUPPCState *env, target_ulong pte_index,
> +                             target_ulong pte0, target_ulong pte1);
> +
>  #else
> 
>  static inline uint32_t kvmppc_get_tbfreq(void)
> @@ -207,6 +210,13 @@ static inline void kvmppc_hash64_free_pteg(uint64_t
> token) abort();
>  }
> 
> +static inline void kvmppc_hash64_write_pte(CPUPPCState *env,
> +                                           target_ulong pte_index,
> +                                           target_ulong pte0,
> target_ulong pte1) +{
> +    abort();
> +}
> +
>  #endif
> 
>  #ifndef CONFIG_KVM
> diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> index fb297d62e3a6..9f5db1b3d9b5 100644
> --- a/target-ppc/mmu-hash64.c
> +++ b/target-ppc/mmu-hash64.c
> @@ -595,3 +595,21 @@ hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState
> *env, target_ulong addr)
> 
>      return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK;
>  }
> +
> +void ppc_hash64_store_hpte(CPUPPCState *env,
> +                           target_ulong pte_index,
> +                           target_ulong pte0, target_ulong pte1)
> +{
> +    if (kvmppc_kern_htab) {
> +        return kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
> +    }
> +
> +    pte_index *= HASH_PTE_SIZE_64;
> +    if (env->external_htab) {
> +        stq_p(env->external_htab + pte_index, pte0);
> +        stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1);
> +    } else {
> +        stq_phys(env->htab_base + pte_index, pte0);
> +        stq_phys(env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1);
> +    }
> +}
> diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
> index 3b6769ad130b..9c9ca1dfe2b5 100644
> --- a/target-ppc/mmu-hash64.h
> +++ b/target-ppc/mmu-hash64.h
> @@ -9,6 +9,8 @@ int ppc_store_slb (CPUPPCState *env, target_ulong rb,
> target_ulong rs); hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env,
> target_ulong addr); int ppc_hash64_handle_mmu_fault(CPUPPCState *env,
> target_ulong address, int rw, int mmu_idx);
> +void ppc_hash64_store_hpte(CPUPPCState *env, target_ulong index,
> +                           target_ulong pte0, target_ulong pte1);
>  #endif
> 
>  /*
> @@ -102,20 +104,6 @@ static inline target_ulong
> ppc_hash64_load_hpte1(CPUPPCState *env, }
>  }
> 
> -static inline void ppc_hash64_store_hpte(CPUPPCState *env,
> -                                         target_ulong pte_index,
> -                                         target_ulong pte0, target_ulong
> pte1) -{
> -    pte_index *= HASH_PTE_SIZE_64;
> -    if (env->external_htab) {
> -        stq_p(env->external_htab + pte_index, pte0);
> -        stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1);
> -    } else {
> -        stq_phys(env->htab_base + pte_index, pte0);
> -        stq_phys(env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1);
> -    }
> -}
> -
>  typedef struct {
>      uint64_t pte0, pte1;
>  } ppc_hash_pte64_t;



-- 
Gregory Kurz                                     address@hidden
                                                 address@hidden
Software Engineer @ IBM/Meiosys                  http://www.ibm.com
Tel +33 (0)562 165 496

"Anarchy is about taking complete responsibility for yourself."
        Alan Moore.