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[Qemu-ppc] [PATCH 13/45] target-ppc: Don't share get_pteg_offset() betwe
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PATCH 13/45] target-ppc: Don't share get_pteg_offset() between 32 and 64-bit |
Date: |
Wed, 6 Mar 2013 14:44:01 +1100 |
The get_pteg_offset() helper function is currently shared between 32-bit
and 64-bit hash mmus, taking a parameter for the hash pte size. In the
64-bit paths, it's only called in one place, and it's a trivial
calculation. This patch, therefore, open codes it for 64-bit. The
remaining version, which is used in two places is made 32-bit only and
moved to mmu-hash32.c.
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 1 -
target-ppc/mmu-hash32.c | 7 ++++++-
target-ppc/mmu-hash32.h | 1 +
target-ppc/mmu-hash64.c | 2 +-
target-ppc/mmu_helper.c | 9 ++-------
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 38ebe2b..bf3ec02 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1154,7 +1154,6 @@ void ppc_hw_interrupt (CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
-hwaddr get_pteg_offset(CPUPPCState *env, hwaddr hash, int pte_size);
int get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong virtual, int rw, int type);
#endif /* !defined(CONFIG_USER_ONLY) */
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index 4b7598b..0ccaf7c 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -174,6 +174,11 @@ static int ppc_hash32_pte_update_flags(mmu_ctx_t *ctx,
target_ulong *pte1p,
return store;
}
+hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
+{
+ return (hash * HASH_PTE_SIZE_32 * 8) & env->htab_mask;
+}
+
/* PTE table lookup */
static int find_pte32(CPUPPCState *env, mmu_ctx_t *ctx, int h,
int rw, int type, int target_page_bits)
@@ -184,7 +189,7 @@ static int find_pte32(CPUPPCState *env, mmu_ctx_t *ctx, int
h,
int ret, r;
ret = -1; /* No entry found */
- pteg_off = get_pteg_offset(env, ctx->hash[h], HASH_PTE_SIZE_32);
+ pteg_off = get_pteg_offset32(env, ctx->hash[h]);
for (i = 0; i < 8; i++) {
if (env->external_htab) {
pte0 = ldl_p(env->external_htab + pteg_off + (i * 8));
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index 9c452b4..0774103 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -1,6 +1,7 @@
#if !defined (__MMU_HASH32_H__)
#define __MMU_HASH32_H__
+hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash);
hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
int mmu_idx);
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index f9c5b09..7134616 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -378,7 +378,7 @@ static int find_pte64(CPUPPCState *env, mmu_ctx_t *ctx, int
h,
int ret, r;
ret = -1; /* No entry found */
- pteg_off = get_pteg_offset(env, ctx->hash[h], HASH_PTE_SIZE_64);
+ pteg_off = (ctx->hash[h] * HASH_PTE_SIZE_64 * 8) & env->htab_mask;
for (i = 0; i < 8; i++) {
if (env->external_htab) {
pte0 = ldq_p(env->external_htab + pteg_off + (i * 16));
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 2deb635..50ec0ac 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -499,11 +499,6 @@ int get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
return ret;
}
-hwaddr get_pteg_offset(CPUPPCState *env, hwaddr hash, int pte_size)
-{
- return (hash * pte_size * 8) & env->htab_mask;
-}
-
/* Perform segment based translation */
static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int type)
@@ -1551,9 +1546,9 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env,
target_ulong address, int rw,
tlb_miss:
env->error_code |= ctx.key << 19;
env->spr[SPR_HASH1] = env->htab_base +
- get_pteg_offset(env, ctx.hash[0], HASH_PTE_SIZE_32);
+ get_pteg_offset32(env, ctx.hash[0]);
env->spr[SPR_HASH2] = env->htab_base +
- get_pteg_offset(env, ctx.hash[1], HASH_PTE_SIZE_32);
+ get_pteg_offset32(env, ctx.hash[1]);
break;
case POWERPC_MMU_SOFT_74xx:
if (rw == 1) {
--
1.7.10.4
- [Qemu-ppc] [0/45] ppc: Clean up hash mmu implementation, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 33/45] mmu-hash32: Clean up BAT matching logic, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 05/45] target-ppc: Disentangle pte_check(), David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 39/45] mmu-hash64: Factor SLB N bit into permissions bits, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 31/45] mmu-hash32: Remove odd pointer usage from BAT code, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 41/45] mmu-hash*: Clean up real address calculation, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 13/45] target-ppc: Don't share get_pteg_offset() between 32 and 64-bit,
David Gibson <=
- [Qemu-ppc] [PATCH 15/45] target-ppc: mmu_ctx_t should not be a global type, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 24/45] mmu-hash*: Cleanup segment-level NX check, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 09/45] target-ppc: Disentangle get_physical_address() paths, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 45/45] mmu-hash64: Implement Virtual Page Class Key Protection, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 11/45] target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug(), David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 38/45] mmu-hash*: Clean up permission checking, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 04/45] target-ppc: Move SLB handling into a mmu-hash64.c, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 02/45] target-ppc: Trivial cleanups in mmu_helper.c, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 01/45] target-ppc: Remove vestigial PowerPC 620 support, David Gibson, 2013/03/05
- [Qemu-ppc] [PATCH 40/45] mmu-hash*: Clean up PTE flags update, David Gibson, 2013/03/05