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[Qemu-ppc] [PATCH 6/6] openpic: s/opp->nb_irqs -1/opp->nb_cpus - 1/
From: |
Scott Wood |
Subject: |
[Qemu-ppc] [PATCH 6/6] openpic: s/opp->nb_irqs -1/opp->nb_cpus - 1/ |
Date: |
Thu, 13 Dec 2012 20:12:04 -0600 |
"opp->nb_irqs-1" would have been a minor coding style error,
but putting in one space but not the other makes it look
confusingly like a numeric literal "-1".
Signed-off-by: Scott Wood <address@hidden>
---
hw/openpic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index c0c4307..debd77d 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -433,8 +433,8 @@ static void openpic_reset(DeviceState *d)
opp->glbc = GLBC_RESET;
/* Initialise controller registers */
- opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) |
- ((opp->nb_cpus -1) << FREP_NCPU_SHIFT) |
+ opp->frep = ((opp->nb_irqs - 1) << FREP_NIRQ_SHIFT) |
+ ((opp->nb_cpus - 1) << FREP_NCPU_SHIFT) |
(opp->vid << FREP_VID_SHIFT);
opp->pint = 0;
--
1.7.9.5
- [Qemu-ppc] [PATCH 0/6] openpic: first batch of cleanups and minor fixes, Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 1/6] openpic: symbolicize some magic numbers, Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 4/6] openpic: don't crash on a register access without a CPU context, Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 5/6] openpic: BRR1 is not a CPU-specific register., Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 2/6] openpic: remove pcsr (CPU sensitivity register), Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 6/6] openpic: s/opp->nb_irqs -1/opp->nb_cpus - 1/,
Scott Wood <=
- [Qemu-ppc] [PATCH 3/6] openpic: support large vectors on FSL mpic, Scott Wood, 2012/12/13
- Re: [Qemu-ppc] [PATCH 0/6] openpic: first batch of cleanups and minor fixes, Alexander Graf, 2012/12/14