[Qemu-ppc] [PATCH v2] openpic: Added BRR1 register

[Bharat Bhushan]

Linux mpic driver uses (changes may be in pipeline to get upstreamed soon)
BRR1. This patch adds the support to emulate readonly BRR1.

Currently QEMU does not fully emulate any version on MPIC, so the MPIC
Major number and Minor number are set to 0.

Signed-off-by: Bharat Bhushan <address@hidden>
---
 hw/openpic.c |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 58ef871..aad2ee9 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -130,6 +130,16 @@ enum {
 #define MPIC_CPU_REG_START        0x20000
 #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
 
+/*
+ * Block Revision Register1 (BRR1): QEMU does not fully emulate
+ * any version on MPIC. So to start with, set the IP version to 0.
+ */
+#define BRR1_IPID 0x00400000 /* IP-block ID */
+#define BRR1_IPMJ 0x00000000 /* IP major number */
+#define BRR1_IPMN 0x00000000 /* IP minor number */
+
+
+
 enum mpic_ide_bits {
     IDR_EP     = 31,
     IDR_CI0     = 30,
@@ -595,6 +605,8 @@ static void openpic_gbl_write (void *opaque, 
target_phys_addr_t addr, uint32_t v
     if (addr & 0xF)
         return;
     switch (addr) {
+    case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
+        break;
     case 0x40:
     case 0x50:
     case 0x60:
@@ -671,6 +683,7 @@ static uint32_t openpic_gbl_read (void *opaque, 
target_phys_addr_t addr)
     case 0x1090: /* PINT */
         retval = 0x00000000;
         break;
+    case 0x00: /* Block Revision Register1 (BRR1) */
     case 0x40:
     case 0x50:
     case 0x60:
@@ -893,6 +906,9 @@ static uint32_t openpic_cpu_read_internal(void *opaque, 
target_phys_addr_t addr,
     dst = &opp->dst[idx];
     addr &= 0xFF0;
     switch (addr) {
+    case 0x00: /* Block Revision Register1 (BRR1) */
+        retval = BRR1_IPID | BRR1_IPMJ | BRR1_IPMN;
+        break;
     case 0x80: /* PCTP */
         retval = dst->pctp;
         break;
-- 
1.7.0.4