Re: [Qemu-ppc] [PATCH] target-ppc: Init dcache and icache size for e500 user mode

[Andreas Färber]

Am 10.04.2012 22:04, schrieb Meador Inge:
> commit f7aa558396dd0f6b7a2b22c05cb503c655854102 pulled the dcache and icache
> line size initialization inside of a '#if !defined(CONFIG_USER_ONLY)' block.
> This is not correct because instructions like 'dcbz' need the dcache size
> initialized even for user mode.
> 
> Signed-off-by: Meador Inge <address@hidden>

Looks okay and compiles,

Reviewed-by: Andreas Färber <address@hidden>

Scott, are you planning to review this e500 patch? Or should I go ahead
and apply?

Andreas

> ---
>  target-ppc/translate_init.c |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index b1f8785..ef8735a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -4466,25 +4466,32 @@ static void init_proc_e500 (CPUPPCState *env, int 
> version)
>      env->nb_pids = 3;
>      env->nb_ways = 2;
>      env->id_tlbs = 0;
> +#endif
>      switch (version) {
>      case fsl_e500v1:
>          /* e500v1 */
> +#if !defined(CONFIG_USER_ONLY)
>          tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
>          tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 
> 16);
> +#endif
>          env->dcache_line_size = 32;
>          env->icache_line_size = 32;
>          break;
>      case fsl_e500v2:
>          /* e500v2 */
> +#if !defined(CONFIG_USER_ONLY)
>          tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
>          tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 
> 16);
> +#endif
>          env->dcache_line_size = 32;
>          env->icache_line_size = 32;
>          break;
>      case fsl_e500mc:
>          /* e500mc */
> +#if !defined(CONFIG_USER_ONLY)
>          tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
>          tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 
> 64);
> +#endif
>          env->dcache_line_size = 64;
>          env->icache_line_size = 64;
>          l1cfg0 |= 0x1000000; /* 64 byte cache block size */
> @@ -4492,7 +4499,6 @@ static void init_proc_e500 (CPUPPCState *env, int 
> version)
>      default:
>          cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", 
> env->spr[SPR_PVR]);
>      }
> -#endif
>      gen_spr_BookE206(env, 0x000000DF, tlbncfg);
>      /* XXX : not implemented */
>      spr_register(env, SPR_HID0, "HID0",

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