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[Qemu-ppc] [PATCH 40/64] PPC: Fix sync instructions problem in SMP
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PATCH 40/64] PPC: Fix sync instructions problem in SMP |
Date: |
Thu, 6 Oct 2011 10:05:42 +0200 |
From: Elie Richa <address@hidden>
In the current emulation of the load-and-reserve (lwarx) and
store-conditional (stwcx.) instructions, the internal reservation
mechanism is taken into account, however each CPU has its own
reservation information and this information is not synchronized between
CPUs to perform proper synchronization.
The following test case with 2 CPUs shows that the semantics of the
"lwarx" and "stwcx." instructions are not preserved by the emulation.
The test case does the following :
- CPU0: reserve a memory location
- CPU1: reserve the same memory location
- CPU0: perform stwcx. on the location
The last store-conditional operation succeeds while it is supposed to
fail since the reservation was supposed to be lost at the second reserve
operation.
This (one line) patch fixes this problem in a very simple manner by
removing the reservation of a CPU every time it is scheduled (in
cpu_exec()). While this is a harsh workaround, it does not affect the
guest code much because reservations are usually held for a very short
time, that is an lwarx is almost always followed by an stwcx. a few
instructions below. Therefore, in most cases, the reservation will be
taken and consumed before a CPU switch occurs. However in the rare case
where a CPU switch does occur between the lwarx and its corresponding
stwcx. this patch solves a potential erroneous behavior of the
synchronization instructions.
Signed-off-by: Elie Richa <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
cpu-exec.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index aef66f2..a9fa608 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -217,6 +217,7 @@ int cpu_exec(CPUState *env)
#elif defined(TARGET_ARM)
#elif defined(TARGET_UNICORE32)
#elif defined(TARGET_PPC)
+ env->reserve_addr = -1;
#elif defined(TARGET_LM32)
#elif defined(TARGET_MICROBLAZE)
#elif defined(TARGET_MIPS)
--
1.6.0.2
- [Qemu-ppc] [PATCH 53/64] openpic: Unfold write_IRQreg, (continued)
- [Qemu-ppc] [PATCH 53/64] openpic: Unfold write_IRQreg, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 35/64] PPC: SPAPR: Use KVM function for time info, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 39/64] pseries: More complete WIMG validation in H_ENTER code, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 43/64] KVM: Update kernel headers, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 51/64] ppc405: use RAM_ADDR_FMT instead of %08lx, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 15/64] PPC: bamboo: Move host fdt copy to target, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 57/64] KVM: Update kernel headers, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 47/64] Implement POWER7's CFAR in TCG, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 49/64] vscsi: send the CHECK_CONDITION status down together with autosense data, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 04/64] PPC: Move openpic to target specific code compilation, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 40/64] PPC: Fix sync instructions problem in SMP,
Alexander Graf <=
- [Qemu-ppc] [PATCH 55/64] PPC: Fix via-cuda memory registration, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 06/64] PPC: Extend MPIC MMIO range, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 50/64] Gdbstub: handle read of fpscr, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 54/64] ppc: move ADB stuff from ppc_mac.h to adb.h, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 41/64] pseries: Add real mode debugging hcalls, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 27/64] device tree: dont fail operations, Alexander Graf, 2011/10/06
- Re: [Qemu-ppc] [PULL 00/64] ppc patch queue 2011-10-06, Blue Swirl, 2011/10/08