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Re: [Qemu-ppc] [PATCH 47/58] Implement POWER7's CFAR in TCG
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 47/58] Implement POWER7's CFAR in TCG |
Date: |
Mon, 19 Sep 2011 16:00:23 +1000 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Sat, Sep 17, 2011 at 05:08:29PM +0000, Blue Swirl wrote:
> On Wed, Sep 14, 2011 at 8:43 AM, Alexander Graf <address@hidden> wrote:
> > From: David Gibson <address@hidden>
> >
> > This patch implements support for the CFAR SPR on POWER7 (Come From
> > Address Register), which snapshots the PC value at the time of a branch or
> > an rfid. The latest powerpc-next kernel also catches it and can show it in
> > xmon or in the signal frames.
> >
> > This works well enough to let recent kernels boot (which otherwise oops
> > on the CFAR access). It hasn't been tested enough to be confident that the
> > CFAR values are actually accurate, but one thing at a time.
>
> This looks accurate at least for the cases covered.
>
> A higher performance implementation could be to only update the
> register lazily when the SPR is read, in most other times CFAR would
> be only stored to DisasContext.
Uh, yeah. I think I'll leave that to someone who actually understands
TCG, rather than just bluffing it.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[Qemu-ppc] [PATCH 37/58] pseries: Add a phandle to the xicp interrupt controller device tree node, Alexander Graf, 2011/09/14
[Qemu-ppc] [PATCH 13/58] PPC: E500: Generate IRQ lines for many CPUs, Alexander Graf, 2011/09/14
[Qemu-ppc] [PATCH 43/58] KVM: Update kernel headers, Alexander Graf, 2011/09/14
[Qemu-ppc] [PATCH 52/58] ppc405: use RAM_ADDR_FMT instead of %08lx, Alexander Graf, 2011/09/14
[Qemu-ppc] [PATCH 11/58] PPC: Bump MPIC up to 32 supported CPUs, Alexander Graf, 2011/09/14
[Qemu-ppc] [PATCH 51/58] Gdbstub: handle read of fpscr, Alexander Graf, 2011/09/14