Re: [Qemu-discuss] Question about ARM64 Generic Timer interrupt emulation on Cortex-A53

[Peter Maydell]

On Mon, 25 Feb 2019 at 16:59, bzt <address@hidden> wrote:
> I can confirm that in target/arm/helper.c line 2416, function
> gt_recalc_timer() ISTATUS is set, IMASK is not set and
> "qemu_set_irq(cpu->gt_timer_outputs[1], 1);" is called. After that I'm
> stuck, because that should call struct IRQState's
> cpu->gt_timer_outputs[1]->handler(), but I failed to find what it is
> initialized to. Only thing I've found is in target/arm/cpu.c line 717
> in function arm_cpu_initfn(), but that does not tell me which function
> is used as a handler for GTIMER_PHYS, so I can't follow that path to
> figure out which IRQ line in which controller to enable.

The handler pointer is initialized when the IRQ line from
the core is wired up to an interrupt controller by the board.
If it's a function pointer, then you can tell what interrupt
controller needs to have an enable bit set by looking at
where that function is in the QEMU sources. If it's NULL,
then the problem is that the board code has not wired the
interrupt line to anything at all. Usually single stepping
through the call to qemu_set_irq() will tell you where
something has gone wrong.

thanks
-- PMM