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Re: [PATCH v4 1/6] target/riscv: add ssu64xl
From: |
Alistair Francis |
Subject: |
Re: [PATCH v4 1/6] target/riscv: add ssu64xl |
Date: |
Fri, 31 Jan 2025 09:51:35 +1000 |
On Thu, Jan 16, 2025 at 4:45 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> ssu64xl is defined in RVA22 as:
>
> "sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must
> be supported)."
>
> This is always true in TCG and it's mandatory for RVA23, so claim
> support for it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 1 +
> tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 398 bytes
> 2 files changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3d4bd157d2..b187ef2e4b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -213,6 +213,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
> ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
> ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
> + ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12),
> ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm),
> ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
> ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
> diff --git a/tests/data/acpi/riscv64/virt/RHCT
> b/tests/data/acpi/riscv64/virt/RHCT
> index
> 695022d56c4ac16607d4c622955ad339fbbfe997..b14ec15e553200760a63aad65586913d31ea2edc
> 100644
> GIT binary patch
> delta 48
> zcmZo;?qlW(@^B96V`N}pOqj@Jz^cQ@$e^;(o|BQSxYW#~B4@H2qXkC_BLhPoBLf2f
> D`wIz-
>
> delta 41
> wcmeBUZe!*O@^B7mV`N}poG_8gfK`Q&kwIpoJtyPj07f&87)Az$G)4vn0JA^`U;qFB
>
> --
> 2.47.1
>
>
- [PATCH v4 0/6] target/riscv: RVA23 profile support, Daniel Henrique Barboza, 2025/01/15
- [PATCH v4 1/6] target/riscv: add ssu64xl, Daniel Henrique Barboza, 2025/01/15
- Re: [PATCH v4 1/6] target/riscv: add ssu64xl,
Alistair Francis <=
- [PATCH v4 2/6] target/riscv: use RVB in RVA22U64, Daniel Henrique Barboza, 2025/01/15
- [PATCH v4 3/6] target/riscv: add profile u_parent and s_parent, Daniel Henrique Barboza, 2025/01/15
- [PATCH v4 4/6] target/riscv: change priv_ver check in validate_profile(), Daniel Henrique Barboza, 2025/01/15
- [PATCH v4 5/6] target/riscv: add RVA23U64 profile, Daniel Henrique Barboza, 2025/01/15
- [PATCH v4 6/6] target/riscv: add RVA23S64 profile, Daniel Henrique Barboza, 2025/01/15